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ST7LITEUS5 数据表(PDF) 85 Page - STMicroelectronics |
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ST7LITEUS5 数据表(HTML) 85 Page - STMicroelectronics |
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85 / 136 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 Instruction set 85/136 11.1.1 Inherent mode All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation. Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word + 2 Relative Direct jrne loop PC-128/PC+1271) + 1 Relative Indirect jrne [$10] PC-128/PC+1271) 00..FF byte + 2 Bit Direct bset $10,#7 00..FF + 1 Bit Indirect bset [$10],#7 00..FF 00..FF byte + 2 Bit Direct Relative btjt $10,#7,skip 00..FF + 2 Bit Indirect Relative btjt [$10],#7,skip 00..FF 00..FF byte + 3 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx. Table 36. ST7 addressing mode overview (continued)(1) Mode Syntax Destination/ source Pointer address Pointer size Length (bytes) Table 37. Instructions supporting inherent addressing mode Inherent instruction Function NOP No operation TRAP S/W Interrupt WFI Wait For Interrupt (low power mode) HALT Halt Oscillator (lowest power mode) RET Subroutine return IRET Interrupt subroutine return SIM Set interrupt mask RIM Reset interrupt mask SCF Set carry flag RCF Reset carry flag RSP Reset stack pointer LD Load CLR Clear PUSH/POP Push/Pop to/from the stack INC/DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 complement MUL Byte multiplication SLL, SRL, SRA, RLC, RRC Shift and rotate operations SWAP Swap nibbles Obsolete Product(s) - Obsolete Product(s) |
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