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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST7LITEUS5 数据表(PDF) 50 Page - STMicroelectronics |
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ST7LITEUS5 数据表(HTML) 50 Page - STMicroelectronics |
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50 / 136 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) Power saving modes ST7LITEUS2, ST7LITEUS5 50/136 Figure 20. Wait mode flowchart 1. 1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. 8.4 Active-halt and Halt modes Active-halt and Halt modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruction. The decision to enter either in Active- halt or Halt mode is given by the LTCSR/ATCSR register status as shown in the following table: WFI INSTRUCTION RESET INTERRUPT Y N N Y CPU OSCILLATOR PERIPHERALS IBIT ON ON 0 OFF FETCH RESET VECTOR OR SERVICE INTERRUPT CPU OSCILLATOR PERIPHERALS IBIT ON OFF 0 ON CPU OSCILLATOR PERIPHERALS IBIT ON ON X 1) ON 64 CPU CLOCK CYCLE DELAY Table 14. Enabling/disabling Active-halt and Halt modes LTCSR TBIE bit ATCSR OVFIE bit ATCSRCK1 bit ATCSRCK0 bit Meaning 0x x0 Active-halt mode disabled 00 x x 0111 1 xxx Active-halt mode enabled x 101 Obsolete Product(s) - Obsolete Product(s) |
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