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ST7LITEUS5 数据表(PDF) 80 Page - STMicroelectronics |
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ST7LITEUS5 数据表(HTML) 80 Page - STMicroelectronics |
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80 / 136 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) On-chip peripherals ST7LITEUS2, ST7LITEUS5 80/136 Figure 36. ADC block diagram Digital A/D conversion result The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (VAIN) is greater than VDDA (high-level voltage reference) then the conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without overflow indication). If the input voltage (VAIN) is lower than VSSA (low-level voltage reference) then the conversion result in the ADCDRH and ADCDRL registers is 00 00h. The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH and ADCDRL registers. The accuracy of the conversion is described in the Electrical Characteristics Section. RAIN is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. A/D conversion phases The A/D conversion is based on two conversion phases: ● Sample capacitor loading [duration: tSAMPLE] During this phase, the VAIN input voltage to be measured is loaded into the CADC sample capacitor. ● A/D conversion [duration: tHOLD] During this phase, the A/D conversion is computed (8 successive approximations CH2 CH1 EOC SPEED ADON 0 CH0 ADCCSR AIN0 AIN1 ANALOG TO DIGITAL CONVERTER AINx ANALOG MUX D4 D3 D5 D9 D8 D7 D6 D2 ADCDRH 3 D1 D0 ADCDRL 00 0 0 SLOW 0 0 RADC CADC HOLD CONTROL fADC fCPU 0 1 1 0 DIV 2 DIV 4 SLOW bit Obsolete Product(s) - Obsolete Product(s) |
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