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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST7LITEUS5 数据表(PDF) 46 Page - STMicroelectronics |
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ST7LITEUS5 数据表(HTML) 46 Page - STMicroelectronics |
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46 / 136 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) Interrupts ST7LITEUS2, ST7LITEUS5 46/136 7.4.3 Low power modes Interrupts The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction). 7.4.4 Register description System Integrity (SI) Control/Status register (SICSR) Reset value: 0000 0x00 (0xh) Table 11. Description of low power modes Mode Description Wait No effect on SI. AVD interrupts cause the device to exit from Wait mode. Halt The SICSR register is frozen. The AVD remains active but the AVD interrupt cannot be used to exit from Halt mode. Table 12. Description of interrupt events Interrupt Event Event flag Enable control bit Exit from Wait Exit from Halt AVD event AVDF AVDIE Yes No 7 0 0 CR1 CR0 0 0 LVDRF AVDF AVDIE Read/write Bit 7 Reserved, must be kept cleared. Bits 6:5 CR[1:0] RC Oscillator Frequency Adjustment bits These bits, as well as CR[9:2] bits in the RCCR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain the required accuracy. Refer to Section 6.2: Internal RC oscillator adjustment on page 28. Bits 4:3 Reserved, must be kept cleared. Obsolete Product(s) - Obsolete Product(s) |
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