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ST7LITEUS5 数据表(PDF) 41 Page - STMicroelectronics |
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ST7LITEUS5 数据表(HTML) 41 Page - STMicroelectronics |
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41 / 136 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 Interrupts 41/136 7.3.1 External Interrupt Control register 1 (EICR1) Reset value: 0000 0000 (00h) Table 9. Interrupt mapping N° Source block Description Register label Priority order Exit from Halt Address vector RESET Reset N/A Highest priority Lowest priority yes FFFEh-FFFFh TRAP Software interrupt no FFFCh-FFFDh 0 AWU Auto-wakeup interrupt AWUCSR yes(1) FFFAh-FFFBh 1 ei0 External interrupt 0 N/A yes FFF8h-FFF9h 2 ei1 External interrupt 1 FFF6h-FFF7h 3 ei2 External interrupt 2 FFF4h-FFF5h 4 Not used no FFF2h-FFF3h 5 ei3 External interrupt 3 yes FFF0h-FFF1h 6 2) ei4 2) External interrupt 4 2) no(2) FFEEh-FFEFh 7 SI AVD interrupt SICSR no FFECh-FFEDh 8 AT TIMER AT TIMER Output Compare Interrupt PWMxCS R or ATCSR no FFEAh-FFEBh 9 AT TIMER Overflow Interrupt ATCSR yes(3) FFE8h-FFE9h 10 LITE TIMER LITE TIMER Input Capture Interrupt LTCSR no FFE6h-FFE7h 11 LITE TIMER RTC1 Interrupt LTCSR yes(3) FFE4h-FFE5h 12 Not used no FFE2h-FFE3h 13 Not used no FFE0h-FFE1h 1. This interrupt exits the MCU from Auto-wakeup from Halt mode only. 2. This interrupt exits the MCU from Wait and Active-halt modes only. Moreover, IS4[1:0] = 01 is the only safe configuration to avoid spurious interrupt in Halt and AWUFH mode 3. These interrupts exit the MCU from Active-halt mode only. 7 0 0 0 IS21 IS20 IS11 IS10 IS01 IS00 Read/Write Bits 7:6 Reserved Bits 5:4 IS2[1:0] ei2 sensitivity These bits define the interrupt sensitivity for ei2 according to Table 10. Bits 3:2 IS1[1:0] ei1 sensitivity These bits define the interrupt sensitivity for ei1 according to Table 10. Bits 1:0 IS0[1:0] ei0 sensitivity These bits define the interrupt sensitivity for ei0 according to Table 10. Obsolete Product(s) - Obsolete Product(s) |
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