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数据搜索系统，热门电子元器件搜索 |
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ST7LITEUS5 数据表(PDF) 70 Page - STMicroelectronics |
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ST7LITEUS5 数据表(HTML) 70 Page - STMicroelectronics |
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70 / 136 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) On-chip peripherals ST7LITEUS2, ST7LITEUS5 70/136 Lite Timer Input Capture register (LTICR) Reset value: 0000 0000 (00h) Bit 2 WDGRF Force Reset/ Reset Status Flag This bit is used in two ways: it is set by software to force a watchdog reset. It is set by hardware when a watchdog reset occurs and cleared by hardware or by software. It is cleared by hardware only when an LVD reset occurs. It can be cleared by software after a read access to the LTCSR register. 0: No watchdog reset occurred. 1: Force a watchdog reset (write), or, a watchdog reset occurred (read). Bit 1 WDGE Watchdog Enable This bit is set and cleared by software. 0: Watchdog disabled 1: Watchdog enabled Bit 0 WDGD Watchdog Reset Delay This bit is set by software. It is cleared by hardware at the end of each tWDG period. 0: Watchdog reset not delayed 1: Watchdog reset delayed 7 0 ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0 Read only Bit 7:0 ICR[7:0] Input capture value These bits are read by software and cleared by hardware after a reset. If the ICF bit in the LTCSR is cleared, the value of the 8-bit up-counter will be captured when a rising or falling edge occurs on the LTIC pin. Table 26. Lite timer register map and reset values Address (Hex.) Register label 7 65 43 2 1 0 0B LTCSR Reset value ICIE 0 ICF 0 TB 0 TBIE 0 TBF 0 WDGRF x WDGE 0 WDGD 0 0C LTICR Reset value ICR7 0 ICR6 0 ICR5 0 ICR4 0 ICR3 0 ICR2 0 ICR1 0 ICR0 0 Obsolete Product(s) - Obsolete Product(s) |
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