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ST7LITEUS5 数据表(PDF) 68 Page - STMicroelectronics |
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ST7LITEUS5 数据表(HTML) 68 Page - STMicroelectronics |
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68 / 136 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) On-chip peripherals ST7LITEUS2, ST7LITEUS5 68/136 10.1.4 Low power modes 10.1.5 Interrupts They generate an interrupt if the enable bit is set in the LTCSR register and the interrupt mask in the CC register is reset (RIM instruction). Figure 32. Input capture timing diagram Table 24. Description of low power modes Mode Description Wait No effect on Lite timer Active-Halt No effect on Lite timer Halt Lite timer stops counting Table 25. Interrupt events(1) 1. The TBF and ICF interrupt events are connected to separate interrupt vectors (see Interrupts chapter). Interrupt event Event flag Enable control bit Exit from Wait Exit from Halt Exit from Active-halt Timebase Event TBF TBIE Yes No Yes IC Event ICF ICIE Yes No No 0004h 13-bit COUNTER t 0001h fOSC xxh 0002h 0003h 0005h 0006h 0007h 04h LTIC PIN ICF FLAG LTICR REGISTER CLEARED 125 ns (@ 8 MHz fOSC) fCPU BY S/W 07h READING LTIC REGISTER Obsolete Product(s) - Obsolete Product(s) |
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