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ST7LITEUS5 数据表(PDF) 115 Page - STMicroelectronics |
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ST7LITEUS5 数据表(HTML) 115 Page - STMicroelectronics |
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115 / 136 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 Electrical characteristics 115/136 Figure 62. RESET pin protection when LVD is disabled 12.10 ADC characteristics Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified. 0.01 μF EXTERNAL RESET CIRCUIT USER Required ST7XXX PULSE GENERATOR Filter RON VDD INTERNAL RESET WATCHDOG ILLEGAL OPCODE 5) Table 66. 10-bit ADC characteristics Symbol Parameter Conditions Min Typ(1) 1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5 V. They are given only as design guidelines and are not tested. Max Unit fADC ADC clock frequency(2) 2. The maximum ADC clock frequency allowed within VDD = 2.4 to 2.7 V operating range is 1 MHz. 4MHz VAIN Conversion voltage range(3) 3. When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS. VSSA VDDA V RAIN External input resistor VDD = 5 V, fADC=4 MHz 8(4) 4. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k Ω). Data based on characterization results, not tested in production. k Ω VDD = 3.3 V, fADC=4 MHz 7(4) 2.7 V ≤ V DD ≤5.5 V, fADC=2 MHz 10(4) 2.4 V ≤ V DD ≤2.7 V, fADC=1 MHz TBD(4) CADC Internal sample and hold capacitor 3pF tSTAB Stabilization time after ADC enable fCPU=8 MHz, fADC=4 MHz 0(5) 5. The stabilization time of the A/D converter is masked by the first tLOAD. The first conversion after the enable is then always valid. μs tADC Conversion time (Sample+Hold) 3.5 - Sample capacitor loading time - Hold conversion time 4 10 1/fADC Obsolete Product(s) - Obsolete Product(s) |
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