AD9925BBCZRL datasheet(33/96 Pages) AD

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AD9925

Rev. A | Page 33 of 96

Table 17. SG Pattern Registers (Also See Field Registers in Table 15)

Length

Range

Description

SGPOL

1 b

High/Low

Sensor Gate Starting Polarity for SG Pattern 0 to 3

SGTOG1

12 b

0 to 4095 Pixel Location

First Toggle Position for SG Pattern 0 to 3

SGTOG2

12 b

0 to 4095 Pixel Location

Second Toggle Position for SG Pattern 0 to 3

SGMASK_OVR

6 b

Six Individual Bits

SG Masking, Overrides the Values in the Field Registers

SGMASKOVR_EN

1 b

Disable/Enable

1: Enables SGMASK Fast Update

PROGRAMMABLE SETTINGS FOR EACH PATTERN:

1. START POLARITY OF PULSE.

2. FIRST TOGGLE POSITION.

3. SECOND TOGGLE POSITION.

4. ACTIVE LINE FOR XSG PULSES WITHIN THE FIELD (PROGRAMMABLE IN THE FIELD REGISTER, NOT FOR EACH PATTERN).

XSG PATTERNS

Figure 42. Vertical Sensor Ga

r to

, rather than having to write in all the vertical

hese three bits. The remaining register bits are

until a new write to the MODE register occurs.

ter settings for

Table 18. MODE Register Data Bit Breakdown (D23 = MSB)

3 D12

D11 D10 D9

D8 D7 D6

D5 D4 D3

D2 D1 D0

te Pulse Placement

which field timing would be active depending on how the camer

was being used. Table 18 shows how the MODE register data

bits are used. The three MSBs, D23 to D21, are used to specify

how many total fields will be used. Any value from 1 to 7 can be

selected using t

D23 D22 D21

D20 D19 D18

D17 D16 D15

D14 D1

MODE Register

The MODE register is a single register that selects the field timing

of the AD9925. Typically, all the field, vertical sequence, and ver-

tical pattern group information is programmed into the AD9925

at startup. During operation, the MODE register allows the use

select any combination of field timing to meet the current requir

ments of the system. The advantage of using the MODE register in

conjunction with preprogrammed timing is that it greatly reduce

the system programming requirements during camera operation.

Only a few register writes are required when the camera operating

mode is changed

timing information with each camera mode change.

A basic still camera application might require five different fiel

of vertical timing: one for draft mode operation, one for auto-

focusing, and three for still image readout. All of the register

timing information for the five fields would be loaded at startup.

Then, during camera operation, the MODE register would select

divided into 3-bit sections to select which of the six fields ar

used and in which order. Up to seven fields may be used in a

single MODE write. The AD9925 will start with the field timin

specified by the first field bits, and on the next VD it will switch

to the timing specified by the second field bits, and so on.

After completing the total number of fields specified in Bits D23

to D21, the AD9925 will repeat by starting at the first field again

This will continue

Figure 43 shows examples of the MODE regis

different field configurations.

Total Number of

Fields to Use

Seventh Field

Sixth Field

Fifth Field

Fourth Field

Third Field

Second Field

First Field

1 = First Field Only

0 = Field 0

7 = All 7 Fields

5 = Field 5

0 = Invalid

6, 7 = Invalid

AD9925BBCZRL 数据表(PDF) 33 Page - Analog Devices

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