AD9925BBCZRL datasheet(53/96 Pages) AD

53 / 96 page

AD9925

Rev. A | Page 53 of 96

Data

Table 33. Power-Up Register Write Sequence

Address

scription

0x10

0x01

Registers to Default Va

set All

lues

0x0A to 0x0D

TBD

Standby V-Driver Input Signal Polarities

0x00

0x04

Power-Up the AFE and CLO Oscillator

0x7F

0x01

Select Register Bank 2

0x00 to 0xFF

TBD

rtical Sequence, and Fi

Tim

AT, Ve

eld

ing

0x7F

0x00

Select Register Bank 1

0x15

0x01

Reset Internal Timing Core

0x31 to 0x71

TBD

l and Shutter Timing

rizonta

0x20

0x01

Configure for Master Mode

0x11

0x01

Enable All Outputs after SYNC

0x13

0x01

SYNCPOL (for Software SYNC Only)

Generating Software SYN

out External SYNC

rnal SYNC pulse is

ailable, it is possible to

nternal SYNC in the AD9925 by writing to the SY

Addr 0x13). If the

re SYNC option is use

ut (Pin J5) should

d to ground (VSS).

After power-up, follow the same procedure as before, for Steps 1

through 11. Then, for Step 12, instead of using the external

SYNC pulse, write a 1 to the SYNCPOL register. This will gen-

erate the SYNC internally, and the timing operation will begin.

SYNC during Master Mode Operation

he SYNC input may be used any time during operation to

resync the AD9925 counters with external timing, as shown in

Figure 68. The operation of the digital outputs may be suspended

during the SYNC operation by setting the SYNCSUSPEND regis-

ter (Addr 0x14) to a 1.

Power-Up and Synchronization in Slave Mode

The power-up procedure for slave mode operation is the same

as the procedure described for master mode operation, with

two exceptions:

Eliminate Step 10. Do not write the part into master mode.

No SYNC pulse is required in slave mode. Substitute Step

12 with starting the external VD and HD signals. This will

synchronize the part, allow the Bank 1 register updates,

and start the timing operation.

ode, the VD and HD in-

re us

nize the intern

ollowing a

falling edg

, there will be a latenc

master clock edges

(CLI) after

lling edge of HD until t

ernal H-Counter is

reset. The r

eration is shown in Fig

Vertical T

emen

Counter Reset

One addit

nsideration during th

f the internal

counters is

tical toggle position pl

nt. Before the in-

ternal coun

e reset, there is an area

ls where no

toggle posi

ould be programmed

For master

the last 18 pixels befo

D falling edge

should not

d for toggle position pl

nt of the XV, XSG,

SUBCK, H

BLK, or CLPOB puls

ure 70).

Figure 71

he same example for sl

de. The same

restriction

the last 18 pixels befo

counters are reset

and canno

ed. However, in slave m

he counter reset is

delayed wi

ect to VD/HD placem

erefore, the inhib-

ited area is

nt than it is in master

Additional Considerations for Toggle Positions

In addition to avoiding toggle position placement near the counter-

reset location, there are a couple of other recommendations.

Pixel location 0 should not be used for any of the toggle positions

for the XSG and SUBCK pulses.

Also, the propagation delay of the V-driver circuit should be con-

sidered when programming the toggle positions for the XV, XSG,

and SUBCK pulses. The delay of the V-driver circuit is specified

in Table 3 and is a maximum of 200 ns.

C with

Signal

If an exte

not av

gener-

ate an i

NCPO

softwa

d, the

SYNC inp

be tie

When the AD9925 is used in slave m

puts a

ed to synchro

al counters. F

e of VD

y of 23

the fa

he int

eset op

ure 69

oggle Position Plac

t near

ional co

e reset o

the ver

aceme

ters ar

of 18 pixe

tions sh

mode,

re the H

be use

aceme

BLK, P

es (see Fig

shows t

ave mo

applies:

re the

t be us

ode, t

th resp

ent; th

differe

mode.

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