AD9925BBCZRL datasheet(52/96 Pages) AD

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AD9925

Rev. A | Page 52 of 96

POWER

SUPPLIES

SERIAL

WRITES

(OUTPUT)

1ST FIELD

SYNC

(INPUT)

DIGITAL

OUTPUTS

CLOCKS ACTIVE WHEN OUT_CONTROL

H1/H3, RG, DCLK

H2/H4

CLI

(INPUT)

(OUTPUT)

tSYNC

VH1 = VH2 = 15

VDVDD = DVDD = DR

VDD = RGVDD = TCVDD = A

VL = –7.5V

.0V

VDD = H

VDD = 3V

Figure 67. Recommended Power-Up Sequence and Synchronization, Master Mode

Recommended Power-Up Sequence for Master Mode

When the AD9925 is powered up, the following sequence is

recommended (refer to Figure 67 for each step). Note that a

SYNC signal is required for master mode operation. If an exter-

nal SYNC pulse is not available, it is also possible to generate an

internal SYNC pulse by writing to the SYNCPOL register, as

described in the next section.

Turn on power supplies for the AD9925 and apply master

clock CLI.

Reset the internal AD9925 registers by writing a 1 to the

SW_RESET register (Addr 0x10 in Bank 1).

Write to the standby mode polarity registers 0x0A to 0x0D

to set the proper polarities for the V-driver inputs, in order

to avoid damage to the CCD. See Table 35 for settings.

The V-driver supplies, VH and VL, can then be powered up

anytime after completing Step 3 to set the proper polarities.

By default, the AD9925 is in standby 3 mode. To place the

part into normal power operation, write 0x004 to the AFE

OPRMODE register (Addr 0x00 in Bank 1).

Write a 1 to the BANKSELECT register (Addr 0×7F)). This

will select Register Bank 2. Load Bank 2 registers with the

required VPAT group, vertical sequence, and field timing

information.

Write a 0 to the BANKSELECT register to select Bank 1.

By default, the internal timing core is held in a reset state

with TGCORE_RSTB register = 0. Write a 1 to the

TGCORE_RSTB register (Addr 0x15 in Bank 1) to start the

internal timing core operation. Note: If a 2x clock is used

for the CLI input, the CLIDIVIDE register (Addr 0x30)

should be set to 1 before resetting the timing core.

Load the required registers to configure the high speed

timing, horizontal timing, and shutter timing information.

10. Configure the AD9925 for master mode timing by writing

a 1 to the MASTER register (Addr 0x20 in Bank 1).

11. Write a 1 to the OUT_CONTROL register (Addr 0x11 in

Bank 1).This will allow the outputs to become active after

the next SYNC rising edge.

12. Generate a SYNC event: If SYNC is high at power-up,

bring the SYNC input low for a minimum of 100 ns. Then

bring SYNC back to high. This will cause the internal

counters to reset and will start the VD/HD operation. The

first VD/HD edge allows most Bank 1 register updates to

occur, including OUT_CONTROL to enable all outputs.

AD9925BBCZRL 数据表(PDF) 52 Page - Analog Devices

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