AD9925BBCZRL datasheet(14/96 Pages) AD

14 / 96 page

AD9925

Rev. A | Page 14 of 96

y, which consists of a CDS, VGA,

tion is

xternal

processor, which will reset internal counters and resync the VD

and HD outputs. The AD9925 also contains an optional reset

pin, RSTB, which may be used to perform an asynchronous

hardware reset function.

SYSTEM OVERVIEW

Figure 14 shows the typical system block diagram for the

AD9925 used in master mode. The CCD output is processed

the AD9925’s AFE circuitr

black level clamp, and ADC. The digitized pixel informa

sent to the digital image processor chip, which performs the

postprocessing and compression. To operate the CCD, all CCD

timing parameters are programmed into the AD9925 from the

system microprocessor through the 3-wire serial interface.

From the system master clock, CLI, provided by the image

processor or external crystal, the AD9925 generates the CCD’s

horizontal and vertical clocks and internal AFE clocks. E

synchronization is provided by a SYNC pulse from the micro

CCDIN

MSHUT

STROBE

H1 TO H4, RG

V1A, V2, V3A, V3B, V4, V5A,

V5B, V6, V7, V8, SUBCK, VSUB

CCD

AD9925

AFETG

V-DRIVER

DIGITAL

IMAGE

PROCESSING

ASIC

DOUT

DCLK

HD, VD

CLI

SERIAL

INTERFACE

SYNC

RSTB

µP

Figure 14. Typical System Block Diagram, Master Mode

AD9925, allowing these clocks t

directly connected to the

CCD. An H-d

d. A high

voltage V-driver is also included for the vertical clocks, allowing

irect connection to the CCD. The SUBCK and VSUB signals

ay require external transistors, depending on the CCD used.

The AD9925 also includes programmable MSHUT and

STROBE outputs, which may be used to trigger mechanical

shutter and strobe (flash) circuitry.

Figure 15 and Figure 16 show the maximum horizontal and

vertical counter dimensions for the AD9925. All internal hori-

zontal and vertical clocking is controlled by these counters to

specify line and pixel locations. Maximum HD length is 8192

pixels per line, and maximum VD length is 4096 lines per field.

Alternatively, the AD9925 may be operated in slave mode, in

which the VD and HD are provided externally from the image

processor. In this mode, all AD9925 timing will be synchro-

nized with VD and HD.

The H-drivers for H1 to H4 and RG are included in the

o be

rive voltage of up to 3.3 V is supporte

13-BIT HORIZONTAL = 8192 PIXELS MAX

12-BIT VERTICAL = 4096 LINES MAX

MAXIMUM

COUNTER

DIMENSIONS

Figure 15. Vertical and Horizontal Counters

MAX VD LENGTH IS 4096 LINES

CLI

MAX HD LENGTH IS 8192 PIXELS

Figure 16. Maximum VD/HD Dimensions

AD9925BBCZRL 数据表(PDF) 14 Page - Analog Devices

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