AD9925BBCZRL datasheet(16/96 Pages) AD

16 / 96 page

AD9925

Rev. A | Page 16 of 96

7. H3 RISING EDGE POSITION AND 8: H3 FALLING EDGE POSITION (H4 I

CCD

SIGNAL

PROGRAMMABLE CLOCK POSITIONS:

1. RG RISING EDGE.

2. RG FALLING EDGE.

3. SHP SAMPLE LOCATION.

4. SHD SAMPLE LOCATION.

5. H1 RISING EDGE POSITION AND 6: H1 FALLING EDGE POSITION (H2 IS INVERSE OF H1).

S INVERSE OF H3).

Figure 18. High Speed Clock Programmable Locations

ws the de

ng locatio

of the high

ck signals.

RG Out

rogra mable timing posi

tpu

vers for the RG

ers are p

erful enough to

CD inputs. The H-driver and RG current can be adjusted for

ptimum rise/fall time with a particular load by using the

RVCONTROL register (Addr x35). The 3-bit drive setting for

each output is adjustable in 4.1 mA increments, with the mini-

mum setting of 0 equal to OFF or three-state and the

etting of 7 equal to 30.1 mA.

20, the H2 and H4

ossover voltage is approximately

e output swing. The

ssover voltage is not programm

ta Outputs

x37, Bits [5:0]). Any

s shown in Figure 21.

in phase,

ut-

put phase can also be held fixed with respect to the data outputs

by changing the DCLKMODE register high (Addr x37, Bit [6]).

In this mode, the DCLK output will remain at a fixed phase

equal to CLO (the inverse of CLI), while the data output phase

is still programmable.

There is a fixed output delay from the DCLK rising edge to the

DOUT transition, called tOD. This delay can be programmed to

four values between 0 ns and 12 ns by using the DOUTDELAY

Bits [8:7]). T

peline delay through the

Figure 22.

he CCD input is sampled

11 cycle

ntil the data is available.

Table 8. Timing Core Register Parameters for H1, H3, RG, SHP/SHD

arameter

Length

Range

Description

Figure 20 sho

fault timi

ns for all

speed clo

H-Driver and

puts

In addition to the p

tions, the AD9925

features on-chip o

puts. These driv

t dri

and H1 to H4 out-

directly drive the

maximum

As shown in Figure 18, Figure 19, and Figure

inverses of H1 and H3,

outputs are

respectively. The H1/H

50% of th

cro

able.

Digital Da

The AD9925 data output and DCLK phase are programmable

using the DOUTPHASE register (Addr

edge from 0 to 47 may be programmed, a

Normally, the DOUT and DCLK signals will track

based on the DOUTPHASE register contents. The DCLK o

he default value is 8 ns

The pi

AD9925 is shown in

After t

by SHD, there is an

delay u

Polarity

1 b

High/Low

Polarity Control for H1, H3, and RG (0 = No Inversion, 1 = Inversion)

Positive Edge

6 b

0 to 47 Edge Location

Positive Edge Location for H1, H3, and RG

Negative Edge

6 b

0 to 47 Edge Location

Negative Edge Location for H1, H3, and RG

Sampling Location

6 b

0 to 47 Edge Location

Sampling Location for Internal SHP and SHD Signals

Drive Strength

3 b

0 to 47 Current Steps

Drive Current for H1 to H4 and RG Outputs (4.1 mA per Step)

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