AD9925BBCZRL datasheet(34/96 Pages) AD

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AD9925

Rev. A | Page 34 of 96

FIELD = FI

LE 3:

ND FIELD = FI

EXAMPLE 1:

TOTAL FIELDS = 3, FIRST FIELD = FIELD 0, SECOND FIELD = FIELD 1, THIRD FIELD = FIELD 2

MODE REGISTER CONTENTS = 0x60 0088

EXAMPLE 2:

TOTAL FIELDS = 2, FIRST FIELD = FIELD 3, SECOND

MODE REGISTER CONTENTS = 0x40 0023

ELD 4

EXAMP

TOTAL FIELDS = 4, FIRST FIELD = FIELD 5, SECO

MODE REGISTER CONTENTS = 0x80 050D

ELD 1, THIRD FIELD = FIELD 4, FOURTH FIELD = FIELD 2

FIELD 3

FIELD 4

FIELD 0

FIELD 1

FIELD 2

FIELD 5

FIELD 1

FIELD 4

FIELD 2

er to Select Field Timing

number of high speed vertical pulses needed to clear any char

Figure 43. Using the M

VERTICAL TIMING EXAMPLE

ODE Regist

ular

determine the line boundaries for each region, and then the

SEQSEL registers assign a particular vertical sequence to each

egion. The vertical sequences contain the specific timing

formation required in each region: XV1 to XV6 pulses (using

PAT groups), HBLK/CLPOB timing, and XSG patterns for the

SG active lines.

This particular timing example requires four regions for each of

the three fields, labeled Region 0, Region 1, Region 2, and

Region 3. Because the AD9925 allows up to six individual fields

to be programmed, the Field 0, Field 1, and Field 2 registers can

be used to meet the requirements of this timing example. The

four regions for each field are very similar in this example, but

the individual registers for each field allow flexibility to accom-

modate other timing charts.

Region 0 is a high speed vertical shift region. Sweep mode may

be used to generate this timing operation, with the desired

ER, SUBCK, VSUB, MSHUT, and STROBE),

nd the AFE gain register. These registers will be explained in

other examples.

Important Note about Signal Polarities

When programming the AD9925 to generate the XV1 to XV8,

XSG1 to XSG6, and SUBCK signals, it is important to note that

the vertical driver circuit will invert these signals. Carefully

check the required timing signals needed at the output of the

vertical driver circuit and adjust the polarities of the XV signals

accordingly.

To better understand how the AD9925 vertical timing generatio

is used, consider CCD timing chart in Figure 44. This partic

example illustrates a CCD using a general 3-field readout tech-

nique. As described in the previous field section, each readout

field should be divided into separate regions to perform each

step of the readout. The sequence change positions (SCP)

from the CCD’s vertical registers. Region 1 consists of only tw

lines and, like Region 3, uses standard single line vertical shift

timing. Region 2 is the sensor gate line, where the VSG pulses

transfer the image into the vertical CCD registers. This region

may require the use of the second vertical pattern group for the

SG active line.

In summary, four regions are required in each of the three

fields. The timing for Region 1 and Region 3 is essentially the

same, reducing the complexity of the register programming.

However, other registers will need to be used during the actual

readout operation, such as the MODE register, shutter control

registers (TRIGG

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