AD9925BBCZRL datasheet(32/96 Pages) AD

32 / 96 page

AD9925

Rev. A | Page 32 of 96

XV1 TO XV8

REGION 1: SWEEP REGION

LINE 0

LINE 1

REGION 0

REGION 2

LINE 24

LINE 25

LINE 2

SCP 1

SCP 2

Figure 40. Example of Sweep Region for High Speed Vertical Shift

XV1 TO XV8

VPATLEN

MULTIPLIER MODE VERTICAL PATTERN GROUP PROPER

1. START POLARITY (ABOVE: STARTPOL =

2. FIRST, SECOND, AND THIRD TOGGLE PO

TIES:

0).

SITIONS (ABOVE: VTOG1 = 2

S IS THE MIN

AY ALSO C

OG × VPAT

, VTOG2 = 9).

IMUM RESOLUTION FOR TOGGLE POSITION CHANGES.

ROSS THE HD BOUNDRIES, AS SHOWN ABOVE.

LEN).

3. LENGTH OF VPAT COUNTER (ABOVE: VPATLEN = 4); THI

5. IF SWEEP REGION IS ENABLED, THE VERTICAL PULSES M

4. TOGGLE POSITIONS OCCUR AT LOCATION EQUAL TO (VT

1234123412

PIXEL

NUMBER

START POSITION OF VPAT GROUP IS STILL PROGRAMMED IN THE VERTICAL SEQUENCE REGISTERS

1234123412

341234123

123456789 10 11 12 13 14 15 16 1

7 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

for Wide Vertical Pulse Timing

Figure 41. Example of Mult

Vertical Sensor Gate (Shift Gate) Patterns

iplier Region

an interline CCD, the sensor gates (SG) are used to transfer

rtica

is then clocked out line-by-line, using the

r puls

spe

ns the

iste

SG o

o XSG6. E

the o

can be assigned to one of four programmed patterns by using

the SGPATSEL registers. Each pattern is generated in a similar

manner as the vertical pattern groups, with a programmable

start polarity (SGPOL), first toggle position (SGTOG1), and

second toggle position (SGTOG2). The active line where the SG

pulses occur is programmable using the SGLINE1 and

SGLINE2 registers. Additionally, any of the XSG1 to XSG6

outputs may be individually disabled by using the SGMASK

ppr

fields can be separately enabled. For maximum flexibility, the

ble f

. Se

lete

in-

Sequ

n f

ils.

rides the SG masking in the field registers (Bank 2). The

SGMASK_OVR register allows sensor gate masking to be

changed without modifying the field register values. Setting the

SGMASKOVR_EN bit high enables the SGMASK override

function. The SGMASK_OVR register is SCK updated, so the

new SG masking values will update immediately.

the pixel charges from the light-sensitive image area into the

light-shielded ve

l registers. From he light-shielded vertical

registers, the image

vertical transfe

es in conjunction with the high

ed hori-

zontal clocks.

Table 17 con

AD9925 has six

tai

summary of t

utputs, XSG1 t

SG pattern reg

ach of

rs. The

utputs

be preprogram ed, and the a

opriate pulses

r the differe

SGPATSEL, SG ASK, and SG INE registers are separately

programma

or each field

e the Comp

Field: Comb

ing Vertical

ences sectio

or more deta

Additionally, t re is a register n Bank 1 (Add 0x55) that over

AD9925BBCZRL 数据表(PDF) 32 Page - Analog Devices

AD9925BBCZRL 数据表(HTML) 32 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

数据表下载