AD9925BBCZRL datasheet(47/96 Pages) AD

47 / 96 page

AD9925

Rev. A | Page 47 of 96

VERTICAL DRIVER SIGNAL CONFIGURATION

As shown in Figure 57, XV1 to XV8, XSG1 to XSG6, and

XSUBCK are outputs from the internal AD9925 timing genera-

tor, while V1 to V8 and SUBCK are the resulting outputs from

the AD9925 vertical driver. The vertical driver performs the

mixing of the XV and XSG pulses and amplifies them to the

high voltages required for driving the CCD. Additionally, the

vertical driver outputs are inverted from the internal XV, XSG,

and SUBCK polarities configured by the AD9925 registers.

Table 22 to Table 32 describe the output polarities for these

signals vs. their input levels. Refer to these tables when deter-

mining the register settings for the desired output levels.

Figure 58 to Figure 64 show graphically the relationship between

the polarities of the XV and XSG signals and the inverted verti-

cal driver output signals.

V3A

V5A

SUBCK

V3B

V5B

INTERNAL

TIMING

GENERATOR

XV1

XV4

XSG1

+3V

VERTICAL DRIVER

+15V, –7.5V

XV6

XV7

XV8

XSUBCK

XV2

XSG6

XV3

XSG2

XSG3

XSG4

XV5

XSG5

G11

G10

H10

K10

AD9925

3-LEVEL OUTPUTS

2-LEVEL OUTPUTS

Figure 57. AD9925 Internal V-Driver Input Signals

AD9925BBCZRL 数据表(PDF) 47 Page - Analog Devices

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