AD9925BBCZRL datasheet(45/96 Pages) AD

45 / 96 page

AD9925

Rev. A | Page 45 of 96

6dB ~ 42dB

CCDIN

DC RESTORE

DIGITAL

FILTER

CLPOB

OPTICAL BLACK

CLAMP

12-BIT

ADC

VGA

DAC

2V FULL SCALE

PRECISION

TIMING

GENERATION

V-H

TIMING

GENERATION

SHP

SHD

DOUT

PHASE

CLPOB

PBLK

AD9925

CDS

SHP

SHD

1.3V

INTERNAL

VREF

REFT

REFB

1.0V

2.0V

0.1

µF

1.0

µF 1.0µF

VGA GAIN

CLAMP LEVEL

OUTPUT

DATA

LATCH

DOUT PHASE

DCLK

DOUT

DLY

DCLK

MODE

FIXED

DELAY

CLI

DOUT

CLI

Figure 55. Analog Front End Functional Block Diagram

ANALOG FRONT END DESCRIPTION

AND OPERATION

The AD9925 signal processing chain is shown in Figure 55.

Each processing step is essential in achieving a high quality

image from the raw CCD pixel data.

DC Restore

To reduce the large dc offset of the CCD output signal, a dc-

restore circuit is used with an external 0.1 µF series coupling

capacitor. This restores the dc level of the CCD signal to ap-

proximately 1.3 V, which allows it to be compatible with the

3 V supply voltage of the AD9925.

Correlated Double Sampler

he CDS circuit samples each CCD pixel twice to extract the

video information and reject the low frequency noise. The timing

shown in Figure 19 illustrates how the two internally generated

CDS clocks, SHP and SHD, are used to sample the reference level

and data level of the CCD signal, respectively. The placement of

the SHP and SHD sampling edges is determined by setting the

SAMPCONTROL register located at Addr 0x36. Placement of

these two clock signals is critical in achieving the best perform-

ance from the CCD.

Variable Gain Amplifier

The VGA stage provides a gain range of 6 dB to 42 dB, program-

mable with 10-bit resolution through the serial digital interface.

The minimum gain of 6 dB is needed to match a 1 V input signal

with the ADC full-scale range of 2 V. When compared to 1 V full-

scale systems, the equivalent gain range is 0 dB to 36 dB.

The VGA gain curve follows a linear-in-dB characteristic. The

exact VGA gain can be calculated for any gain register value by

using the equation

Gain (dB) = (0.0351 × Code) + 6 dB

ange is 0 to 1023.

where the Code r

VGA GAIN REGISTER CODE

127

255

383

511

639

767

895

1023

Figure 56. VGA Gain Curve

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