AD9925BBCZRL datasheet(63/96 Pages) AD

63 / 96 page

AD9925

Rev. A | Page 63 of 96

Table 39. VD/HD Register Map

Address

Data Bit Content

Default Value

[0]

MASTER

VD/HD Master or Slave Timing (0 = Slave Mode).

[0]

VDHDPOL

VD/HD Active Polarity. 0 = Low and 1 = High.

[11:0]

HDRISE

[17:12]

VDRISE

Rising Edge Location for HD.

r VD.

Rising Edge Location fo

[11:0]

SCP0

SCP0. Used for All Fields.

Table 40. Timing Core Register Map

Address

Data Bit Content

Default Value

[0]

CLIDIVIDE

Divide CLI Input Clock by 2. 1 = Divide by 2.

[0]

[6:1]

[12:7]

H1POL

H1POSLOC

H1NEGLOC

H1 Polarity. 0: Inversion, 1: No Inversion.

H1 Positive Edge Location.

H1 Negative Edge Location.

[0]

[6:1]

[12:7]

H3POL

H3POSLOC

H3NEGLOC

H3 Polarity. 0: Inversion, 1: No Inversion.

H3 Positive Edge Location.

H3 Negative Edge Location.

[0]

[6:1]

[12:7]

RGPOL

RGPOSLOC

RGNEGLOC

RG Polarity. 0: Inversion, 1: No Inversion.

RG Positive Edge Location.

RG Negative Edge Location.

[0]

[1]

H1RETIME

H3RETIME

Retime H1/H3 HBLK to Internal H1/H3 Clocks. Preferred setting is 1

for each bit, which adds one cycle of delay to the programmed HBLK

toggle positions.

[2:0]

[5:3]

[8:6]

[11:9]

[14:12]

H1DRV

H2DRV

H3DRV

H4DRV

RGDRV

Drive Strength Control for H1.

0: Off.

1: 4.3 mA.

2: 8.6 mA.

3: 12.9 mA.

4: 17.2 mA.

5: 21.5 mA.

6: 25.8 mA.

7: 30.1 mA.

Drive Strength Control for H2 (Same Values as H1DRV).

Drive Strength Control for H3 (Same Values as H1DRV).

Drive Strength Control for H4 (Same Values as H1DRV).

Drive Strength Control for RG (Same Values as H1DRV).

[5:0]

[11:6]

SHPLOC

SHDLOC

SHP Sampling Location.

SHD Sampling Location.

[5:0]

[6]

[8:7]

DOUTPHASE

DCLKMODE

DOUTDLY

DOUT Phase Control.

0: DCLK Tracks DOUTPHASE.

1: DCLK Does Not Track DOUTPHASE, Remains Fixed with Regards to

CLI

Data Output Delay (tOD) with Respect to DCLK.

0: No Delay, 1: ~4 ns, 2: ~8 ns, and 3: ~12 ns.

[2:0]

HBLKWIDTH

Controls HBLK Width as a Fraction of H1 to H4 Frequency.

0: same, 1: 1/2, 2: 1/4, 3: 1/6, 4: 1/8, 5: 1/10, 6: 1/12, and 7: 1/14.

Table 41. CLPOB Masking Register Map

Address

Data Bit Content

Default Value

[11:0]

[23:12]

FFF

CLPMASK0

CLPMASK1

CLPOB Line Masking Line No. 0, or Mask0 Range, Start Line

CLPOB Line Masking Line No. 1, or Mask0 Range, End Line

[11:0]

[23:12]

FFF

CLPMASK2

CLPMASK3

CLPOB Line Masking Line No. 2, or Mask1 Range, Start Line

CLPOB Line Masking Line No. 3, or Mask1 Range, End Line

[11:0]

FFF

CLPMASK4

CLPOB Line Masking Line No. 4, or Mask2 Range, Start Line

[11:0]

[12]

FFF

CLPMASK5

CLPMASKTYPE

CLPOB Line Masking Line No. 5, or Mask2 Range, End Line

0: CLPOB Line Masking, 1: Enable CLPOB Range Masking

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