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AD9925BBCZRL 数据表(PDF) 65 Page - Analog Devices

部件名 AD9925BBCZRL
功能描述  CCD Signal Processor with Vertical Driver and Precision Timing Generator
PDF  96 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9925BBCZRL 数据表(HTML) 65 Page - Analog Devices

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AD9925
Rev. A | Page 65 of 96
Table 44. Register Map Selection
Address
Data Bit Content
Default Value
Register Name
Register Description
7F
[1:0]
0
BANKSELECT
Register Bank Access for Bank 1, Bank 2, and Bank 3.
0: Bank 1, 1: Bank 2, 2: Bank 3, and 3: Bank 1.
Table 45. AFE Operation Register Detail
ress
t Content
fault Value
Add
Data Bi
De
Name
Description
00
[1:0]
3
PWRDOWN
0: Normal Operation, 1: Standby 1, 2: Standby 2, 3: Standby 3.
[2]
1
CLPENABLE
0: Disable OB Clamp, 1: Enable OB Clamp.
[3]
0
CLPSPEED
0: Select Normal OB Clamp Settling, 1: Select Fast OB Clamp
Settling.
[4]
0
FASTUPDATE
1: Select Temporary Fast Clamping When VGA Gain Is Up-
dated.
[5]
0
PBLK_LVL
DOUT Value during PBLK: 0: Blank to 0, 1: Blank to Clamp
Level.
[7:6]
0
TEST
Test Operation Only. Set to 0.
[8]
0
DCBYP
0: Enable DC Restore Circuit, 1: Bypass DC Restore Circuit dur-
ing PBLK.
[9]
0
TEST
Test Use Only. Set to 0.
[11:10]
0
CDSGAIN
0: 0 dB, 1: 2 dB, 2: 4 dB, and 3: 0 dB.
46. A
trol Registe
etail
ress
t Content
fault Value
Table
FE Con
r D
Add
Data Bi
De
Name
Description
03
[1:0]
0
TEST
Test Use Only. Set to 0.
[2]
1
TEST
Test Use Only. Recommended setting is 0.
[3]
0
DOUTDISABLE
0 = Data Outputs Are Driven,
1 = Data Outputs Are Three-Stated.
[4]
0
DOUTLATCH
0 = Latch Data Outputs with DOUT Phase,
1 = Output Latch Transparent.
[5]
0
GRAYENCODE
0 = Binary Encode Data Outputs,
1 = Gray Encode Data Outputs.



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