AD9925BBCZRL datasheet(29/96 Pages) AD

29 / 96 page

AD9925

Rev. A | Page 29 of 96

sequence is used during each region. Registers to control the

XSG outputs are also included in the field registers.

Table 15 summarizes the registers used to create the different

fields. Up to six different fields can be preprogrammed using

the field registers.

The VEQSEL registers, one for each region, select which of the

10 vertical sequences will be active during each region. The

SWEEP registers are used to enable the sweep mode during any

region. The MULTI registers are used to enable the multiplier

mode during any region. The SCP registers create the line

is specified in the vertical sequence registers, but

he HDLAST register specifies the number of pixels in the last

ne of the field. Note that the 13th bit (MSB) of the last line

length is located in a separate register. During the sensor gate

(SG) line, the VPATSECOND register is used to add a second

vertical pattern group to the XV outputs.

The SGMASK register is used to enable or disable each individual

VSG output. There is a single bit for each XSG output, setting

the bit high will mask the output and setting it low will enable

the output. The SGPAT register assigns one of the four different

SG patterns to each VSG output. The individual SG patterns are

created separately using the SG pattern registers. The SGLINE1

outputs. The optional SGLINE2 register allows the same SG pulses

to be repeated on a different line.

Table 15. Field Registers

Length

Range

Description

Complete Field: Combining Vertical Sequences

After the vertical sequences have been created, they are combined

to create different readout fields. A field consists of up to seven

different regions, and within each region, a different vertic

sequence can be selected. Figure 37 shows how the sequence

change positions (SCP) designate the line boundary for each

region, and how the VSEQSEL registers select which vertical

boundaries for each region. The VDLEN register specifies the

total number of lines in the field. The total number of pixels per

line (HDLEN)

VSEQSEL

4 b

0 to 9 V Sequence Number

Selected Vertical Sequence for Each Region in the Field.

SWEEP

1 b

High/L

n Set High.

Enables Sweep Mode for Each Region, Whe

MULTI

1 b

High/Low

Enabl

ultiplier Mode for Each Region, When Set High.

es M

SCP

12 b

0 to 4095 Line Number

Sequence Change Position for Each Region.

VDLEN

12 b

0 to 4095 Number of Lines

Total Number of Lines in Each Field.

HDLAST

13 b

0 to 8191 Num

Each Field. The13th bit (MSB) is located

in a separate register to maintain compatibility with the AD9995.

ber of Pixels

Length in Pixels of the Last HD Line in

VPATSECOND

4 b

0 to 9 Vertical Pattern Group

Number

Selected Vertical Pattern Group for Second Pattern Applied During SG Line.

SGMASK

6 b

High/Low, Each XSG

Set High to Mask Each Individual XSG Output.

XSG1 [0], XSG2 [1], XSG3 [2], XSG4 [3], XSG5 [4], XSG6 [5].

SGPATSEL

12 b

0 to 3 Pattern Number, Each XSG

Selects the SG Pattern Number for Each XSG Output.

XSG1 [1:0], XSG2 [3:2], XSG3 [5:4], XSG4 [7:6], XSG5 [9:8], XSG6 [11:10].

SGLINE1

12 b

0 to 4095 Line Number

Selects the Line in the Field Where the SG Signals Are Active.

SGLINE2

12 b

0 to 4095 Line Number

Selects a Second Line in the Field to Repeat the SG Signals.

REGION 0

FIELD SETTINGS:

1. SEQUENCE CHANGE POSITIONS (SCP1 TO SCP6) DEFINE EACH OF THE SEVEN REGIONS IN THE FIELD.

2. VSEQSEL0 TO VSEQSEL6 SELECTS THE DESIRED VERTICAL SEQUENCE

XV1 TO XV6

SCP 1

SCP 2

VSEQSEL0

VSEQSEL1

SCP 3

VSEQSEL2

SCP 4

VSEQSEL3

SCP 5

VSEQSEL4

SCP 6

VSEQSEL5

VSEQSEL6

REGION 1

REGION 2

REGION 3

REGION 4

REGION 5

REGION 6

XSG

SGLINE

3. SGLINE1 REGISTER SELECTS WHICH HD LINE IN THE FIELD WILL CONTAIN THE SENSOR GATE PULSE(S).

(0–9) FOR EACH REGION.

Figure 37. Complete Field Is Divided into Regions

AD9925BBCZRL 数据表(PDF) 29 Page - Analog Devices

AD9925BBCZRL 数据表(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

数据表下载

链接网址

AD9925BBCZRL 数据表(PDF) 29 Page - Analog Devices

AD9925BBCZRL 数据表(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

数据表 下载

链接网址

数据表下载