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LSM6DSOP 数据表(PDF) 51 Page - STMicroelectronics |
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LSM6DSOP 数据表(HTML) 51 Page - STMicroelectronics |
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51 / 107 page  DocID032926 Rev 5 51/107 LSM6DSOP Register description 107 9.7 COUNTER_BDR_REG1 (0Bh) Counter batch data rate register 1 (r/w) Table 32. COUNTER_BDR_REG1 register description 9.8 COUNTER_BDR_REG2 (0Ch) Counter batch data rate register 2 (r/w) Table 34. COUNTER_BDR_REG2 register description Table 31. COUNTER_BDR_REG1 register dataready _pulsed RST_ COUNTER _BDR TRIG_ COUNTER _BDR 0(1) 1. This bit must be set to '0' for the correct operation of the device. 0(1) CNT_BDR _TH_10 CNT_BDR _TH_9 CNT_BDR _TH_8 dataready_pulsed Enables pulsed data-ready mode (0: Data-ready latched mode (returns to 0 only after an interface reading) (default); 1: Data-ready pulsed mode (the data ready pulses are 75 μs long) RST_ COUNTER_BDR Resets the internal counter of batching events for a single sensor. This bit is automatically reset to zero if it was set to ‘1’. TRIG_ COUNTER_BDR Selects the trigger for the internal counter of batching events between XL and gyro. (0: XL batching event; 1: GYRO batching event) CNT_BDR_TH_ [10:8] In conjunction with CNT_BDR_TH_[7:0] in COUNTER_BDR_REG2 (0Ch), sets the threshold for the internal counter of batching events. When this counter reaches the threshold, the counter is reset and the COUNTER_BDR_IA flag in FIFO_STATUS2 (3Bh) is set to ‘1’. Table 33. COUNTER_BDR_REG2 register CNT_BDR _TH_7 CNT_BDR _TH_6 CNT_BDR _TH_5 CNT_BDR _TH_4 CNT_BDR _TH_3 CNT_BDR _TH_2 CNT_BDR _TH_1 CNT_BDR _TH_0 CNT_BDR_ TH_[7:0] In conjunction with CNT_BDR_TH_[10:8] in COUNTER_BDR_REG1 (0Bh), sets the threshold for the internal counter of batching events. When this counter reaches the threshold, the counter is reset and the COUNTER_BDR_IA flag in FIFO_STATUS2 (3Bh) is set to ‘1’. |
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