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LSM6DSOP 数据表(PDF) 75 Page - STMicroelectronics |
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LSM6DSOP 数据表(HTML) 75 Page - STMicroelectronics |
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75 / 107 page  DocID032926 Rev 5 75/107 LSM6DSOP Register description 107 9.44 INT_PD_CFG (62h) INT pull-down register (r/w) Table 120. INT_PD_CFG register description 9.45 INTERNAL_FREQ_FINE (63h) Internal frequency register (r) Table 122. INTERNAL_FREQ_FINE register description 9.46 X_OFS_USR (73h) Accelerometer X-axis user offset correction (r/w). The offset value set in the X_OFS_USR offset register is internally subtracted from the acceleration value measured on the X-axis. Table 119. INT_PD_CFG register 0(1) 1. This bit must be set to '0' for the correct operation of the device. 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) PD_DIS_ INT PD_DIS_INT This bit allows disabling the INT pull-down. (0: Pull-down on INT enabled (pull-down is effectively connected only when no interrupts are routed to the INT pin); 1: Pull-down on INT disabled (pull-down not connected). Table 121. INTERNAL_FREQ_FINE register FREQ_ FINE7 FREQ_ FINE6 FREQ_ FINE5 FREQ_ FINE4 FREQ_ FINE3 FREQ_ FINE2 FREQ_ FINE1 FREQ_ FINE0 FREQ_FINE[7:0] Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.15%. 8-bit format, 2's complement. Table 123. X_OFS_USR register X_OFS_ USR_7 X_OFS_ USR_6 X_OFS_ USR_5 X_OFS_ USR_4 X_OFS_ USR_3 X_OFS_ USR_2 X_OFS_ USR_1 X_OFS_ USR_0 Table 124. X_OFS_USR register description X_OFS_USR_ [7:0] Accelerometer X-axis user offset correction expressed in two’s complement, weight depends on USR_OFF_W in CTRL6_C (15h). The value must be in the range [-127 127]. |
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