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LSM6DSOP 数据表(PDF) 97 Page - STMicroelectronics |
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LSM6DSOP 数据表(HTML) 97 Page - STMicroelectronics |
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97 / 107 page  DocID032926 Rev 5 97/107 LSM6DSOP Embedded functions register description 107 11.32 EMB_FUNC_ODR_CFG_B (5Fh) Finite State Machine output data rate configuration register (r/w). Table 204. EMB_FUNC_ODR_CFG_B register description 11.33 EMB_FUNC_INIT_B (67h) Embedded functions initialization register (r/w) Table 206. EMB_FUNC_INIT_B register description Table 203. EMB_FUNC_ODR_CFG_B register 0(1) 1. This bit must be set to '0' for the correct operation of the device. 1(2) 2. This bit must be set to '1' for the correct operation of the device. 0(1) FSM_ ODR1 FSM_ ODR0 0(1) 1(2) 1(2) FSM_ODR[1:0] Finite State Machine ODR configuration: (00: 12.5 Hz; 01: 26 Hz (default); 10: 52 Hz; 11: 104 Hz) Table 205. EMB_FUNC_INIT_B register 0(1) 1. This bit must be set to '0' for the correct operation of the device. 0(1) 0(1) 0(1) FIFO_ COMPR_ INIT 0(1) 0(1) FSM_INIT FIFO_COMPR_INIT FIFO compression feature initialization request. Default value: 0 FSM_INIT FSM initialization request. Default value: 0 |
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