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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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RA4M1 数据表(PDF) 117 Page - Renesas Technology Corp |
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RA4M1 数据表(HTML) 117 Page - Renesas Technology Corp |
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117 / 130 page  R01DS0355EJ0100 Rev.1.00 Page 117 of 130 Oct 8, 2019 RA4M1 Group 2. Electrical Characteristics 2.17.1 Serial Wire Debug (SWD) Figure 2.87 SWD SWCLK timing Table 2.78 SWD characteristics (1) Conditions: VCC = 2.4 to 5.5 V Parameter Symbol Min Typ Max Unit Test conditions SWCLK clock cycle time tSWCKcyc 80 - - ns Figure 2.87 SWCLK clock high pulse width tSWCKH 35 - - ns SWCLK clock low pulse width tSWCKL 35 - - ns SWCLK clock rise time tSWCKr -- 5 ns SWCLK clock fall time tSWCKf -- 5 ns SWDIO setup time tSWDS 16 - - ns Figure 2.88 SWDIO hold time tSWDH 16 - - ns SWDIO data delay time tSWDD 2 - 70 ns Table 2.79 SWD characteristics (2) Conditions: VCC = 1.6 to 2.4 V Parameter Symbol Min Typ Max Unit Test conditions SWCLK clock cycle time tSWCKcyc 250 - - ns Figure 2.87 SWCLK clock high pulse width tSWCKH 120 - - ns SWCLK clock low pulse width tSWCKL 120 - - ns SWCLK clock rise time tSWCKr -- 5 ns SWCLK clock fall time tSWCKf -- 5 ns SWDIO setup time tSWDS 50 - - ns Figure 2.88 SWDIO hold time tSWDH 50 - - ns SWDIO data delay time tSWDD 2 - 150 ns SWCLK tSWCKcyc tSWCKH tSWCKf tSWCKr tSWCKL |
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