DSPIC33EP64GS708 datasheet(118/484 Pages) MICROCHIP

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dsPIC33EPXXXGS70X/80X FAMILY

DS70005258C-page 118

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10.2.1

SLEEP MODE

The following occurs in Sleep mode:

• The system clock source is shut down. If an

on-chip oscillator is used, it is turned off.

• The device current consumption is reduced to a

minimum, provided that no I/O pin is sourcing

current.

• The Fail-Safe Clock Monitor does not operate,

since the system clock source is disabled.

• The LPRC clock continues to run in Sleep mode if

the WDT is enabled.

• The WDT, if enabled, is automatically cleared

prior to entering Sleep mode.

• Some device features or peripherals can continue

to operate. This includes items such as the Input

Change Notification on the I/O ports or peripherals

that use an external clock input.

• Any peripheral that requires the system clock

source for its operation is disabled.

The device wakes up from Sleep mode on any of the

these events:

• Any interrupt source that is individually enabled

• Any form of device Reset

• A WDT time-out

On wake-up from Sleep mode, the processor restarts

with the same clock source that was active when Sleep

mode was entered.

For optimal power savings, the internal regulator and

the Flash regulator can be configured to go into stand-

by when Sleep mode is entered by clearing the VREGS

(RCON<8>) and VREGSF (RCON<11>) bits (default

configuration).

If the application requires a faster wake-up time, and

can accept higher current requirements, the VREGS

(RCON<8>) and VREGSF (RCON<11>) bits can be set

to keep the internal regulator and the Flash regulator

active during Sleep mode.

10.2.2

IDLE MODE

The following occurs in Idle mode:

• The CPU stops executing instructions.

• The WDT is automatically cleared.

• The system clock source remains active. By

default, all peripheral modules continue to operate

normally from the system clock source, but can

also be selectively disabled (see Section 10.4

“Peripheral Module Disable”).

• If the WDT or FSCM is enabled, the LPRC also

remains active.

The device wakes from Idle mode on any of these

events:

• Any interrupt that is individually enabled

• Any device Reset

• A WDT time-out

On wake-up from Idle mode, the clock is reapplied to

the CPU and instruction execution will begin (two to

four clock cycles later), starting with the instruction

following the PWRSAV instruction or the first instruction

in the ISR.

All peripherals also have the option to discontinue

operation when Idle mode is entered to allow for

increased power savings. This option is selectable in

the control register of each peripheral (for example, the

TSIDL bit in the Timer1 Control register (T1CON<13>).

10.2.3

INTERRUPTS COINCIDENT WITH

POWER SAVE INSTRUCTIONS

Any interrupt that coincides with the execution of a

PWRSAV instruction is held off until entry into Sleep or

Idle mode has completed. The device then wakes up

from Sleep or Idle mode.

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