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DSPIC33EP64GS708 数据表(PDF) 114 Page - Microchip Technology |
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DSPIC33EP64GS708 数据表(HTML) 114 Page - Microchip Technology |
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114 / 484 page  dsPIC33EPXXXGS70X/80X FAMILY DS70005258C-page 114 2016-2018 Microchip Technology Inc. REGISTER 9-5: ACLKCON: AUXILIARY CLOCK DIVISOR CONTROL REGISTER R/W-0 R-0 R/W-1 U-0 U-0 R/W-1 R/W-1 R/W-1 ENAPLL APLLCK SELACLK — — APSTSCLR2 APSTSCLR1 APSTSCLR0 bit 15 bit 8 R/W-0 R/W-1 U-0 U-0 U-0 U-0 U-0 U-0 ASRCSEL FRCSEL — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ENAPLL: Auxiliary PLL Enable bit 1 = APLL is enabled 0 = APLL is disabled bit 14 APLLCK: APLL Locked Status bit (read-only) 1 = Indicates that Auxiliary PLL is in lock 0 = Indicates that Auxiliary PLL is not in lock bit 13 SELACLK: Select Auxiliary Clock Source for Auxiliary Clock Divider bit 1 = Auxiliary oscillators provide the source clock for the auxiliary clock divider 0 = Primary PLL (FVCO) provides the source clock for the auxiliary clock divider bit 12-11 Unimplemented: Read as ‘0’ bit 10-8 APSTSCLR<2:0>: Auxiliary Clock Output Divider bits 111 = Divided by 1 110 = Divided by 2 101 = Divided by 4 100 = Divided by 8 011 = Divided by 16 010 = Divided by 32 001 = Divided by 64 000 = Divided by 256 bit 7 ASRCSEL: Select Reference Clock Source for Auxiliary Clock bit 1 = Primary oscillator is the clock source 0 = No clock input is selected bit 6 FRCSEL: Select Reference Clock Source for Auxiliary PLL bit 1 = Selects the FRC clock for Auxiliary PLL 0 = Input clock source is determined by the ASRCSEL bit setting bit 5-0 Unimplemented: Read as ‘0’ |
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