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DSPIC33EP64GS708 数据表(PDF) 112 Page - Microchip Technology

部件名 DSPIC33EP64GS708
功能描述  16-Bit Digital Signal Controllers for Digital Power Applications with Interconnected High-Speed PWM, ADC, PGA and Comparators
PDF  484 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

DSPIC33EP64GS708 数据表(HTML) 112 Page - Microchip Technology

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dsPIC33EPXXXGS70X/80X FAMILY
DS70005258C-page 112
 2016-2018 Microchip Technology Inc.
bit 4-0
PLLPRE<4:0>: PLL Phase Detector Input Divider Select bits (also denoted as ‘N1’, PLL prescaler)
11111 = Input divided by 33
•
•
•
00001 = Input divided by 3
00000 = Input divided by 2 (default)
REGISTER 9-2:
CLKDIV: CLOCK DIVISOR REGISTER (CONTINUED)
Note 1:
The DOZE<2:0> bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to
DOZE<2:0> are ignored.
2:
This bit is cleared when the ROI bit is set and an interrupt occurs.
3:
The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to
set the DOZEN bit is ignored.
REGISTER 9-3:
PLLFBD: PLL FEEDBACK DIVISOR REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
PLLDIV8
bit 15
bit 8
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
PLLDIV<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-9
Unimplemented: Read as ‘0’
bit 8-0
PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier)
111111111 = 513
•
•
•
000110000 = 50 (default)
•
•
•
000000010 = 4
000000001 = 3
000000000 = 2



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