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DSPIC33EP64GS708 数据表(PDF) 110 Page - Microchip Technology |
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DSPIC33EP64GS708 数据表(HTML) 110 Page - Microchip Technology |
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110 / 484 page  dsPIC33EPXXXGS70X/80X FAMILY DS70005258C-page 110 2016-2018 Microchip Technology Inc. bit 4 Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Detect bit(3) 1 = FSCM has detected a clock failure 0 = FSCM has not detected a clock failure bit 2-1 Unimplemented: Read as ‘0’ bit 0 OSWEN: Oscillator Switch Enable bit 1 = Requests oscillator switch to the selection specified by the NOSC<2:0> bits 0 = Oscillator switch is complete REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED) Note 1: Writes to this register require an unlock sequence. 2: Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transitional clock source between the two PLL modes. 3: This bit should only be cleared in software. Setting the bit in software (= 1) will have the same effect as an actual oscillator failure and will trigger an oscillator failure trap. |
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