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DSPIC33EP64GS708 数据表(PDF) 106 Page - Microchip Technology |
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DSPIC33EP64GS708 数据表(HTML) 106 Page - Microchip Technology |
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106 / 484 page ![]() dsPIC33EPXXXGS70X/80X FAMILY DS70005258C-page 106 2016-2018 Microchip Technology Inc. FIGURE 9-1: OSCILLATOR SYSTEM DIAGRAM XTPLL, HSPLL, XT, HS, EC FRCDIV<2:0> WDT, PWRT, FRCDIVN FRCDIV16 ECPLL, FRCPLL NOSC<2:0> FNOSC<2:0> Reset LPRC Oscillator DOZE<2:0> S3 S1 S2 S1/S3 S7 S6 FRC LPRC S0 S5 Clock Switch S0 Clock Fail ÷ 2 TUN<5:0> PLL FCY(2) FOSC Note 1: See Figure 9-2 for the source of the FVCO signal. 2: FP refers to the clock source for all the peripherals, while FCY (or MIPS) refers to the clock source for the CPU. Throughout this document, FCY and FP are used interchangeably, except in the case of Doze mode. FP and FCY will be different when Doze mode is used in any ratio other than 1:1. 3: The auxiliary clock postscaler must be configured to divide-by-1 (APSTSCLR<2:0> = 111) for proper operation of the PWM and ADC modules. FSCM ACLK POSCCLK SELACLK FVCO(1) ASRCSEL ENAPLL APLL x 16 POSCCLK FRCCLK FVCO(1) ÷ N APSTSCLR<2:0>(4) FRCCLK FRCSEL OSC2 OSC1 Primary Oscillator (POSC) POSCMD<1:0> FP(2) AUXILIARY CLOCK GENERATOR CIRCUIT BLOCK DIAGRAM 1 0 1 0 1 0 0 1 GND PWM/ADC REFERENCE CLOCK OUTPUT POSCCLK ROSEL FOSC ÷ N RPn REFCLKO RODIV<3:0> to LFSR ÷ 16 FPLLO FRC Oscillator |
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