DSPIC33EP64GS708 datasheet(107/484 Pages) MICROCHIP

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DS70005258C-page 107

dsPIC33EPXXXGS70X/80X FAMILY

9.1

CPU Clocking System

The dsPIC33EPXXXGS70X/80X family of devices

provides six system clock options:

• Fast RC (FRC) Oscillator

• FRC Oscillator with Phase-Locked Loop

(FRCPLL)

• FRC Oscillator with Postscaler

• Primary (XT, HS or EC) Oscillator

• Primary Oscillator with PLL (XTPLL, HSPLL,

ECPLL)

• Low-Power RC (LPRC) Oscillator

Instruction execution speed or device operating

frequency, FCY, is given by Equation 9-1.

EQUATION 9-1:

DEVICE OPERATING

FREQUENCY

Figure 9-2 is a block diagram of the PLL module.

Equation 9-2 provides the relationship between Input

Frequency (FIN) and Output Frequency (FPLLO).

Equation 9-3 provides the relationship between Input

Frequency (FIN) and VCO Frequency (FVCO).

FIGURE 9-2:

PLL BLOCK DIAGRAM

EQUATION 9-2:

FPLLO CALCULATION

EQUATION 9-3:

FVCO CALCULATION

FCY = FOSC/2

÷ N1

÷ M

÷ N2

PFD

VCO

PLLPRE<4:0>

PLLDIV<8:0>

PLLPOST<1:0>

0.8 MHz < FPLLI(1) < 8.0 MHz

120 MHZ < FVCO(1) < 340 MHZ

FPLLO(1)

 120 MHz @ +125ºC

FIN

FPLLI

FVCO

FOSC

Note 1: This frequency range must be met at all times.

FPLLO(1)

 140 MHz @ +85ºC

Where:

N1 = PLLPRE<4:0> + 2

N2 = 2 x (PLLPOST<1:0> + 1)

M = PLLDIV<8:0> + 2

FPLLO = FIN



PLLDIV<8:0> + 2

(PLLPRE<4:0> + 2)

2(PLLPOST<1:0> + 1)





()

() = FIN 

FVCO = FIN



PLLDIV<8:0> + 2

(PLLPRE<4:0> + 2)

()

() = FIN 

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