DSPIC33EP64GS708 datasheet(109/484 Pages) MICROCHIP

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DS70005258C-page 109

dsPIC33EPXXXGS70X/80X FAMILY

9.5

Oscillator Control Registers

OSCCON: OSCILLATOR CONTROL REGISTER(1)

U-0

R-0

U-0

R/W-y

—

COSC2

COSC1

COSC0

—NOSC2(2)

NOSC1(2)

NOSC0(2)

bit 15

bit 8

R/W-0

R-0

U-0

R/W-0

U-0

R/W-0

CLKLOCK

IOLOCK

LOCK

—CF(3)

—

OSWEN

bit 7

bit 0

Legend:

y = Value set from Configuration bits on POR

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

COSC<2:0>: Current Oscillator Selection bits (read-only)

111 = Fast RC Oscillator (FRC) with Divide-by-n

110 = Fast RC Oscillator (FRC) with Divide-by-16

101 = Low-Power RC Oscillator (LPRC)

100 = Reserved

011 = Primary Oscillator (XT, HS, EC) with PLL

010 = Primary Oscillator (XT, HS, EC)

001 = Fast RC Oscillator (FRC) with Divide-by-N and PLL (FRCPLL)

000 = Fast RC Oscillator (FRC)

bit 11

Unimplemented: Read as ‘0’

bit 10-8

NOSC<2:0>: New Oscillator Selection bits(2)

111 = Fast RC Oscillator (FRC) with Divide-by-n

110 = Fast RC Oscillator (FRC) with Divide-by-16

101 = Low-Power RC Oscillator (LPRC)

100 = Reserved

011 = Primary Oscillator (XT, HS, EC) with PLL

010 = Primary Oscillator (XT, HS, EC)

001 = Fast RC Oscillator (FRC) with Divide-by-N and PLL (FRCPLL)

000 = Fast RC Oscillator (FRC)

bit 7

CLKLOCK: Clock Lock Enable bit

1 = If (FCKSM0 = 1), then clock and PLL configurations are locked; if (FCKSM0 = 0), then clock and

PLL configurations may be modified

0 = Clock and PLL selections are not locked, configurations may be modified

bit 6

IOLOCK: I/O Lock Enable bit

1 = I/O lock is active

0 = I/O lock is not active

bit 5

LOCK: PLL Lock Status bit (read-only)

1 = Indicates that PLL is in lock or PLL start-up timer is satisfied

0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled

Note 1:

Writes to this register require an unlock sequence.

Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not

permitted. This applies to clock switches in either direction. In these instances, the application must switch

to FRC mode as a transitional clock source between the two PLL modes.

This bit should only be cleared in software. Setting the bit in software (= 1) will have the same effect as an

actual oscillator failure and will trigger an oscillator failure trap.

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