ADP5014ACPZ-R7 datasheet(28/34 Pages) AD

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ADP5014

Data Sheet

Rev. A | Page 28 of 34

SELECTING THE OUTPUT CAPACITOR

The output capacitor must meet the output voltage ripple and

load transient requirements. To meet the output voltage ripple

requirement, use the following equation to calculate the ESR

and capacitance:

RIPPLE

OUT

RIPPLE

OUT

∆

RIPPLE

OUT

ESR

∆

The calculated capacitance, COUT_RIPPLE, is 19.8 µF, and the

calculated RESR is 5 mΩ.

To meet the ±5% overshoot and undershoot requirements,

use the following equations to calculate the capacitance:

(

)

OUT

STEP

OUT

∆

−

∆

(

)

OUT

OUT_OV

OUT

STEP

OUT

−

∆

For estimation purposes, use KOV = KUV = 2; therefore,

COUT_OV = 62.4 µF and COUT_UV = 20.2 µF.

The ESR of the output capacitor must be less than 5 mΩ,

and the output capacitance must be greater than 62.4 µF. It is

recommended that two ceramic capacitors be used (47 µF, X5R,

6.3 V), such as the GRM21BR60J476ME15 from Murata with

an ESR of 2 mΩ.

DESIGNING THE COMPENSATION NETWORK

For better load transient and stability performance, set the cross

frequency, fC, to fSW/10. In this example, fSW is set to 1.2 MHz;

therefore, fC is set to 120 kHz.

For the 1.2 V output rail, the 47 μF ceramic output capacitor has

a derated value of 32 µF.

Ω

A/V

800

kHz

120

(

)

001

Ω

001

Ω

Choose standard components: RC = 3.57 kΩ and CC = 5.6 nF.

CCP is optional.

Figure 41 shows the bode plot for the 1.2 V output rail. The

cross frequency is 132 kHz, and the phase margin is 56°. The

load transient waveform is shown in Figure 42.

120

100

–20

–40

–60

–80

–100

–120

120

100

–20

–40

–60

–80

–100

–120

10k

100k

FREQUENCY (Hz)

CROSS FREQUENCY = 132kHz

PHASE MARGIN = 56°

Figure 41. Bode Plot for 1.2 V Output

CH1 5.00mV

CH4 2A

M100µs

A CH4

2.16A

25.8%

Ω

Figure 42. Selecting the Input Capacitor

For the input capacitor, select a ceramic capacitor with a

minimum value of 10 µF. The input capacitor is placed close to

the PVINx pin. In this example, one ceramic capacitor of 10 µF,

X5R, 16 V is recommended.

LOW NOISE OUTPUT DESIGN

The ADP5014 optimizes many analog blocks and uses new unity-

gain reference architecture to achieve lower output noise in low-

frequency range. When the system design needs the low noise

output of ADP5014 , the device enables powering up the signal

chain products directly without LDOs. In this scenario, adding

an additional LC filter is highly recommended after the main

LC filter to filter the fundamental switching ripple and its

harmonic. This is because the switching ripples may generate

unexpected noise spurs for the noises sensitive signal chain

devices. Because this additional inductor filter may generate

voltage drop at the load, the inductor with small DCR is

recommended to minimize the voltage drop, especially for high

current applications.

Figure 43 and Figure 44 show the ADP5014 noise spectral

density measurement from a 10 Hz to 10 MHz frequency range

and integrated rms noise from a 10 Hz to 1 MHz frequency

range, compared to the ADP1740 as another traditional, 2 A,

low noise linear regulator.

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