ADP5014ACPZ-R7 datasheet(19/34 Pages) AD

19 / 34 page

Data Sheet

ADP5014

Rev. A | Page 19 of 34

Phase Shift

By default, the phase shift between Channel 1 and Channel 2 and

between Channel 3 and Channel 4 is 180° (see Figure 35). This

value provides the benefits of out of phase operation by reducing

the input ripple current and lowering the grounding noise.

CH 2

CH 1

CH 3

CH 4

180° PHASE SHIFT

0° REFERENCE

180° PHASE SHIFT

0° REFERENCE

Figure 35. Phase Shift Diagram, Four Buck Regulators

SYNCHRONIZATION INPUT/OUTPUT

The GPIO pin can be configured as the synchronization clock

input by using the CFG2 pin (see Table 7), and the switching

frequency of the ADP5014 can be synchronized to an external

clock with a frequency range from 500 kHz to 2.5 MHz. The

ADP5014 automatically detects the presence of an external

clock applied to the GPIO pin, and the switching frequency

transitions smoothly to the frequency of the external clock.

When the external clock signal stops, the device automatically

switches back to the internal clock and continues to operate.

The internal switching frequency set by the RT pin must be

programmed to a value that is close to the external clock value

for successful synchronization; the suggested frequency

difference is less than ±15% in typical applications.

The GPIO pin can be configured as a push/pull synchronization

clock output by CFG2 (refer to Table 7). A positive clock pulse

with a 50% duty cycle is generated at the GPIO pin with a

frequency equal to the internal switching frequency set by the

RT pin.

Figure 36 shows two ADP5014 devices configured for frequency

synchronization mode: one ADP5014 device is configured as

the clock output to synchronize another ADP5014 device.

GPIO

CFG

(CLOCK MASTER)

(SLAVE)

ADP5014

DEVICE 2

ADP5014

DEVICE 1

(CLK-OUT) (SYNC-IN)

CFG2

Figure 36. Two ADP5014 Devices Configured for Synchronization Mode

In the configuration shown in Figure 36, the phase shift

between Channel 1 of the first ADP5014 device and Channel 1

of the second ADP5014 device is 0˚.

POWER-GOOD FUNCTION

The ADP5014 GPIO pin can be configured as an open-drain

power-good output (PWRGD pin) that becomes active high

when the selected buck regulators are operating normally.

A high status in the PWRGD pin indicates that the regulated

output voltage of the buck regulator is above 90% (typical) of its

nominal output. When the regulated output voltage of the buck

regulator falls below 87% (typical) of its nominal output for a

delay time greater than approximately 50 µs, the status of the

PWRGD pin is set to low.

The output of the PWRGD pin is the logical AND of the internal

PWRGD signals on an individual channel. An internal PWRGD

signal on an individual channel must be high for a validation

time of 2 ms (typical) timer before the PWRGD pin goes high.

This validation timer can be increased by 8 times (×8 option)

using the CFG2 pin configuration; if one internal PWRGD fails,

the PWRGD pin goes low with no delay.

UV COMPARATOR (SEQUENCE MODE ONLY)

In sequence mode, the EN3/UV pin is used as the UVO input

(UV pin), while the ADP5014 GPIO pin can be configured as

an open-drain UVO via CFG2 pin configuration. The UV

comparator is not related to the channel enabling and is only

used for monitoring purposes. For example, it can be used to

monitor any output voltage to create a power-good signal in

sequence mode.

Similar to the precision enable functionality, this UVO features

the same precise 0.6 V reference voltage with the 1 µA or 4 µA

pull-down hysteresis current. Using the ratio of external resistor

divider to program the UVLO threshold allows monitoring

either input voltage or output voltage while using the absolute

value of the external resistor divider to program the hysteresis

window. The UV pin is connected to the input supply if it is not

intended for use. Figure 37 shows the UVO diagram.

0.6V

1µA

3µA

–

PVIN

UVO

RTOP

RBOT

Figure 37. Undervoltage Comparator Diagram (in Sequence Mode Only)

ADP5014ACPZ-R7 数据表(PDF) 19 Page - Analog Devices

ADP5014ACPZ-R7 数据表(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

数据表下载

链接网址

ADP5014ACPZ-R7 数据表(PDF) 19 Page - Analog Devices

ADP5014ACPZ-R7 数据表(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

数据表 下载

链接网址

数据表下载