ADP5014ACPZ-R7 datasheet(22/34 Pages) AD

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ADP5014

Data Sheet

Rev. A | Page 22 of 34

APPLICATIONS INFORMATION

ADIsimPOWER DESIGN TOOL

The ADP5014 is supported by the ADIsimPower™ design tool

set. ADIsimPower is a collection of tools that produce complete

power designs optimized for a specific design goal. The tools

enable the user to generate a full schematic and bill of materials

and to calculate performance in minutes. ADIsimPower can

optimize designs for cost, area, efficiency, and device count

while considering the operating conditions and limitations of the

IC and all real external components. The ADIsimPower tool can

be found at http://www.analog.com/ADIsimPower; the user

can request an unpopulated board through the tool.

PROGRAMMING THE OUTPUT VOLTAGE

The output voltage of the ADP5014 is externally set by a resistive

voltage divider from the VREF pin to the VSETx pin and a

resistive voltage divider from the output voltage to the FBx pin.

To limit the degradation of the output voltage accuracy due to

VSETx and FBx bias current, ensure the value of the bottom

resistor in the dividers is not too large.

The ADP5014 provides adjustable output voltage settings. Use

the resistor divider from the accurate internal VREF reference

voltage (VREF pin) to set the desired output voltage and

directly tie the FBx pin to the output when the desired output

voltage setting is less than the VREF voltage, as shown in Figure 38.

The equation for the output voltage setting is

VOUT = VREF × (R2/(R1+R2))

where:

VOUT is the output voltage.

VREF is the 2.0 V accurate low noise reference voltage.

R2 is the resistor from VSETx to ground.

R1 is the resistor from VSETx to VREF.

If the desired output voltage exceeds the VREF voltage, use an

external resistor divider from the output to the FBx pin to set

the desired output voltage, and tie VSETx to VREF directly, as

shown in Figure 39.

The equation for the output voltage setting is as follows:

VOUT = VREF × (1 + (RTOP/RBOT))

where:

VOUT is the output voltage.

VREF is the 2.0 V accurate low noise reference voltage.

RTOP is the feedback resistor from VOUT to FB.

RBOT is the feedback resistor from FB to ground.

VOLTAGE CONVERSION LIMITATIONS

For a given input voltage, lower limitations on the output voltage

exist due to the minimum on time and the minimum off time.

The minimum output voltage for a given input voltage and

switching frequency is limited by the minimum on time. The

minimum on time for each channel is 60 ns (typical). The

minimum on time increases at higher junction temperatures.

Note that in FPWM mode, the output voltage potentially

exceeds the nominal output voltage when the minimum on

time limit is reached. Careful switching frequency selection is

required to avoid this problem.

The minimum output voltage in CCM mode for a given input

voltage and switching frequency is calculated using the

following equation:

VOUT_MIN = VIN × tMIN_ON × fSW − (RDSON1 − RDSON2) ×

IOUT_MIN × tMIN_ON × fSW − (RDSON2 + RL) × IOUT_MIN

(1)

where:

VOUT_MIN is the minimum output voltage.

tMIN_ON is the minimum on time.

fSW is the switching frequency.

RDSON1 is the high-side MOSFET on resistance.

RDSON2 is the low-side MOSFET on resistance.

IOUT_MIN is the minimum output current.

RL is the resistance of the output inductor.

VSETx

ADP5014

FBx

SWx

VOUTx

COMPx

VREF

–

INTERNAL

REFERENCE 2.0V

Figure 38. Configure the Output Voltage when VOUTx ≤ VREF

–

INTERNAL

REFERENCE 2.0V

VSETx

ADP5014

FBx

SWx

VOUTx

COMPx

VREF

RTOP

RBOT

Figure 39. Configure the Output Voltage when VOUTX > VREF

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