ADP5014ACPZ-R7 datasheet(18/34 Pages) AD

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ADP5014

Data Sheet

Rev. A | Page 18 of 34

Table 9. Setting Sequence Timer in the DL12 and DL34 Pins

RDL12

(or RDL34)

(kΩ)

Channel 1 Sequence

(or Channel 3)

Channel 2 Sequence

(or Channel 4)

First order

Second order

12.1

First order

Third order

14.7

First order

Fourth order

17.8

Second order

First order

21.5

Second order

26.1

Second order

Third order

31.6

Second order

Fourth order

38.3

Third order

First order

46.4

Third order

Second order

56.2

Third order

Float

Third order

Fourth order

68.1

Fourth order

First order

82.5

Fourth order

Second order

100

Fourth order

Third order

121

Fourth order

Note that the RDL12 and RDL34 resistors must have ±1 % tolerance

to ensure the correct decoding result.

The power-up and power-down delay timer for all channels is

designed in an opposite manner to meet typical system

sequence requirements, as described below:

•

First order sequence means the channel is configured as

the first to be powered up, and is shut down last.

•

Second order sequence means the channel is configured as

the second to be powered up and is shut down third.

•

Third order sequence means the channel is configured as

the third to be powered up and is shut down second.

•

Fourth order sequence means the channel is configured as

the fourth to be powered up and is shut down first.

If a longer sequence timer is required, the delay time for all

channels can be increased by 8 times (×8 option) using the

CFG2 pin. Table 10 shows the power-up and power-down timer

configurations.

In sequence enable mode, the device performs the following

actions in fault conditions:

•

During individual fault conditions, such as overcurrent

hiccup, OVP, or PVINx, UVLO shuts down and powers up

the corresponding channel immediately without the

sequence delay.

•

TSD fault shuts down all channels immediately without the

sequence delay, but occurs after the defined power-up

sequence for the recovery.

•

An AVIN UVLO fault shuts down all channels immediately

without any sequence delay, but occurs after the defined

power-up sequence for the recovery after the device

reinitiation.

Table 10. Power-Up and Power-Down Timer

Sequence

Order

Power-Up Delay Timer

(tEN_DLYx)

Power-Down Delay

Timer (tDIS_DLYx)

First Order

0 ms

36 ms (288 ms at

×8 option)

Second

Order

6 ms (48 ms at ×8 option)

24 ms (192 ms at

×8 option)

Third Order

12 ms (96 ms at ×8

option)

12 ms (96 ms at

×8 option)

Fourth

Order

18 ms (144 ms at ×8

option)

0 ms

GENERAL PURPOSE INPUT/OUTPUT (GPIO)

The ADP5014 includes one GPIO pin which can be configured

for different functionalities, such as PWRGD, synchronization

clock input (SYNC-IN), CLK-OUT, or UVO.

The PWRGD and UVO output functionalities have the open-

drain output after the initiation.

The CLK-OUT output functionality features a push/pull output,

enabling it to drive other regulators after initiation.

OSCILLATOR

The switching frequency (fSW) of the ADP5014 can be set to a

value from 500 kHz to 2.5 MHz by connecting a resistor from

the RT pin to ground. Calculate the value of the RT resistor

(RRT) as follows:

RRT (kΩ) = 100,000/fSW (kHz)

Figure 34 shows the typical relationship between fSW and the RT

resistor. The adjustable frequency allows users to make decisions

based on the trade-off between efficiency and the size of the

solution.

2700

2400

2100

1800

1500

1200

900

600

300

100

140

RT RESISTOR (k

Ω)

180

220

Figure 34. Switching Frequency vs. RT Resistor

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