ADP5014ACPZ-R7 datasheet(17/34 Pages) AD

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Data Sheet

ADP5014

Rev. A | Page 17 of 34

Manual Mode (Precision Enable)

In manual mode, the ADP5014 has an individual precision

enable pin for each regulator. The enable control pin (ENx)

features a precision enable circuit with a 0.6 V reference

voltage. When the voltage at the ENx pin is greater than 0.6 V

(typical), the regulator is enabled. When the ENx pin voltage

falls below 0.57 V (typical), the regulator is disabled. To force

the regulator to automatically start up when input power is

applied, connect the enable pin to the input.

The precision enable pin has an internal pull-down current

source (4 μA) that provides a default turn off when the enable

pin is left open. When the enable pin exceeds 0.6 V (typical),

the regulator is enabled and the internal pull-down current

source at the enable pin decreases to 1 μA. The decrease in the

current source allows the ratio of the external resistor divider to

program the UVLO threshold to monitor either the input

voltage or the output voltage while using the absolute value of

external resistor divider to program the hysteresis window.

Figure 32 shows the precision enable diagram.

0.6V

1µA

3µA

EN_CMP

–

RTOP_EN

RBOT_EN

Figure 32. Precision Enable Diagram for One Channel

Sequence Mode

In sequence mode, all channels in the ADP5014 turn on and off

under the control of the internal sequencer, which is triggered

by the ENALL pin. The DL12 and DL34 pins set the predefined

delay timer.

The ENALL pin features precision enable circuitry with a 0.6 V

turn on threshold and internal pull-down current source.

When the ENALL pin goes above the 0.6 V precision threshold,

all channels controlled by the sequencer begin a soft start after

the delay time specified by the DL12 and DL34 pin configuration.

Similarly, when the ENALL pin falls below 0.57 V precision

threshold, the channels turns off after the delay time specified

by DL12 and DL34 pin configurations.

Figure 33 shows the logical states of each channel and does not

show soft start and discharge ramps. Although the output

discharge switch helps to discharge the output capacitor quickly,

the discharge ramps on the output of each channel are still

decided by many different factors, including the output

capacitance, system load, and the ramps of input supply.

DL12 configures the delay timer for Channel 1 and Channel 2 by

connecting one resistor to ground. Similarly, DL34 configures the

delay timer for Channel 3 and Channel 4 (see Table 9). In parallel

operation, the slave channel (Channel 2 or Channel 4) always

follows up with the delay timer configuration of the master

channel; therefore, Channel 2 follows Channel 1, while Channel 4

follows Channel 3. The delay timer decoder circuitry only works

in the initiation stage of the ADP5014; therefore, the delay

timer does not change in operation.

ENALL

EN_DLY2

tEN_DLY1

tEN_DLY3

tEN_DLY4

tDIS_DLY1

tDIS_DLY2

DIS_DLY3

DIS_DLY4

OFF

CHANNEL1

CHANNEL2

CHANNEL3

CHANNEL4

Figure 33. Power-Up/Power-Down in Sequence Enable Mode

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