Data Sheet

ADP5014

Rev. A | Page 31 of 34

TYPICAL APPLICATION CIRCUITS

1.5µH

10nF

L1

GPIO

AVIN

FB1

SW1

SW1

L3

SW3

FB3

PGND3

L4

SW4

FB4

PGND4

PVIN1

PVIN1

PVIN2

PVIN2

PVIN3

COMP3

PVIN4

5.0V

VOUT1

VOUT3

VOUT4

AGND

EXPOSED PAD

ADP5014

PGND1

PGND1

L2

FB2

SW2

SW2

VOUT2

PGND2

EN3/UV

EN2/DL12

EN1/ENALL

EN4/DL34

VREF

CFG1

CFG2

RT

REF

OSC

LOGIC DECODER

C3

47µF

1.2V/4A

2.5V/2A

1.5V/2A

3.3V/2A

0.47µF

0Ω

0.8µH

0.8µH

1.5µH

C7

47µF

C10

47µF

C12

47µF

4.32k

Ω

C1

10µF

C2

1µF

10nF

13.3kΩ

COMP1

VSET1

VREF

20k

Ω

4.32k

Ω

10nF

COMP2

VSET2

VREF

4.32k

Ω

10nF

COMP4

VSET4

VREF

6.65kΩ VSET3

VREF

20k

Ω

6.04k

Ω

CH 1

BUCK

(2A/4A)

CH 2

BUCK

(2A/4A)

CH 3

BUCK

(1A/2A)

CH 4

BUCK

(1A/2A)

C4

47µF

C8

47µF

82.5k

Ω

C6

10µF

C9

10µF

C11

10µF

VCORE

AUXILIARY

VOLTAGE

FPGA

VREF

ENALL

2ms

6ms

12ms

24ms

36ms

12ms

C5

47µF

31.6kΩ

4.99kΩ

20kΩ

0Ω

26.1kΩ

1.2V

2.5V/1.5V

3.3V

I/Os

BANK 0

BANK 1

BANK 2

I/Os

BANK 3

PGND2

13kΩ

20kΩ

DDR

TERM. LDO

DDR3 MEMORY

FLASH MEMORY

Figure 46. Typical Field Programmable Gate Array (FPGA) Application, 1.2 MHz Switching Frequency, Sequence Enable Mode