数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

ADP5014ACPZ-R7 数据表(PDF) 15 Page - Analog Devices

部件名 ADP5014ACPZ-R7
功能描述  Integrated Power Solution with Quad Low Noise Buck Regulators
PDF  34 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP5014ACPZ-R7 数据表(HTML) 15 Page - Analog Devices

Back Button ADP5014ACPZ-R7 Datasheet HTML 11Page - Analog Devices ADP5014ACPZ-R7 Datasheet HTML 12Page - Analog Devices ADP5014ACPZ-R7 Datasheet HTML 13Page - Analog Devices ADP5014ACPZ-R7 Datasheet HTML 14Page - Analog Devices ADP5014ACPZ-R7 Datasheet HTML 15Page - Analog Devices ADP5014ACPZ-R7 Datasheet HTML 16Page - Analog Devices ADP5014ACPZ-R7 Datasheet HTML 17Page - Analog Devices ADP5014ACPZ-R7 Datasheet HTML 18Page - Analog Devices ADP5014ACPZ-R7 Datasheet HTML 19Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 15 / 34 page
background image
Data Sheet
ADP5014
Rev. A | Page 15 of 34
FUNCTION CONFIGURATIONS (CFG1 AND CFG2)
The ADP5014 include CFG1 and CFG2 pins to decode the
function configurations for all channels. The CFG1 pin has a
logic status of 8 that is decoded by connecting one resistor to
ground, whereas the CFG2 pin has a logic status of 16, decoded by
connecting one resistor to ground. This decoder circuitry only
works in the initiation stage of the ADP5014; therefore, the
configurations cannot be changed in operation. Typically, the
chip initiation takes less than 1 ms before the enabled regulator
starts switching.
The CFG1 pin can be used to program the load output capability
and parallel operation for all channels. Table 6 provides the
values of the resistors needed to set different functionality in the
CFG1 pin.
Table 6. Configuration by the CFG1 Pin
RCFG1 (kΩ)
Output Capability
Channel 1
Channel 2
Channel3
Channel 4
0
4 A
4 A
2 A
2 A
10
4 A
2 A
2 A
2 A
12.1
4 A
2 A
1 A
1 A
14.7
2 A
2 A
2 A
2 A
17.8
2 A
2 A
1 A
1 A
21.5
Parallel 8A
Parallel 8 A
2 A
2 A
26.1
4 A
4 A
Parallel 4 A
Parallel 4 A
31.6
Parallel 8 A
Parallel 8 A
Parallel 4 A
Parallel 4 A
The CFG2 pin can be used to program the operation mode
(FPWM or PWM/PSM mode), the enable mode (manual mode
or sequence mode), the timer (×1 or ×8), and GPIO
functionalities (PWRGD, SYNC-IN, CLK-OUT, UVO) for all
channels. Table 7 provides the values of the resistors needed to
set different functionality in the CFG2 pin.
The RCFG1 and RCFG2 resistors must have ±1% tolerance to ensure
the correct decoding result.
Table 7. Configuration by the CFG2 Pin
RCFG2
(kΩ)
Enable
Mode
Timer
Operation
Mode
GPIO
0
Manual
×1
FPWM
PWRGD
10
Manual
×1
FPWM
SYNC-IN
12.1
Manual
×1
FPWM
CLK-OUT
14.7
Manual
×1
PSM
PWRGD
Float
Manual
×8
FPWM
PWRGD
17.8
Manual
×8
FPWM
SYNC-IN
21.5
Manual
×8
FPWM
CLK-OUT
26.1
Manual
×8
PSM
PWRGD
31.6
Sequence
×1
FPWM
UVO
38.3
Sequence
×1
FPWM
SYNC-IN
46.4
Sequence
×1
FPWM
CLK-OUT
56.2
Sequence
×1
PSM
UVO
68.1
Sequence
×8
FPWM
UVO
82.5
Sequence
×8
FPWM
SYNC-IN
100
Sequence
×8
FPWM
CLK-OUT
121
Sequence
×8
PSM
UVO



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com