ADP5014ACPZ-R7 datasheet(14/34 Pages) AD

14 / 34 page

ADP5014

Data Sheet

Rev. A | Page 14 of 34

THEORY OF OPERATION

The ADP5014 is a power management unit that combines four

high performance, low noise buck regulators in a 40-lead LFCSP

package.

BUCK REGULATOR OPERATIONAL MODES

PWM Mode

In PWM mode, the buck regulators in the ADP5014 operate at

a fixed frequency; this frequency is set by an internal oscillator

that is programmed by the RT pin. At the start of each

oscillator cycle, the high-side MOSFET switch turns on and sends

a positive voltage across the inductor. The inductor current

increases until the current sense signal exceeds the peak

inductor current threshold that turns off the high-side

MOSFET switch. This threshold is set by the error amplifier

output. During the high-side MOSFET off time, the inductor

current decreases through the low-side MOSFET switch until

the next oscillator clock pulse starts a new cycle. The buck

regulators in the ADP5014 regulate the output voltage by

adjusting the peak inductor current threshold.

PSM Mode

To achieve higher efficiency, the buck regulators in the

ADP5014 smoothly transition to variable frequency PSM mode

operation when the output load falls below the PSM current

threshold. When the output voltage falls below regulation, the

buck regulator enters PWM mode for a few oscillator cycles

until the voltage increases to within regulation. During the idle

time between bursts, the MOSFET switch turns off, and the

output capacitor supplies all the output current.

The PSM mode comparator monitors the internal compensation

node, which represents the peak inductor current information.

The average PSM mode current threshold depends on the input

voltage (VIN), the output voltage (VOUT), the inductor, and the

output capacitor. Because the output voltage occasionally falls

below regulation and then recovers, the output voltage ripple in

PSM mode is larger than the ripple in the forced PWM mode of

operation under light load conditions.

FPWM and Automatic PWM/PSM Modes

The buck regulators can be configured to always operate in FPWM

mode using the CFG2 configuration pin. In forced PWM mode,

the regulator continues to operate at a fixed frequency even when

the output current is below the PWM/PSM threshold. In PWM

mode, the efficiency is lower compared to PSM mode under light

load conditions. The low-side MOSFET remains on when the

inductor current falls to less than 0 A, causing the ADP5014 to

enter continuous conduction mode (CCM).

The buck regulators can be configured to operate in automatic

PWM or PSM mode using the CFG2 configuration pin. In

automatic PWM/PSM mode, the buck regulators operate in

either PWM mode or PSM mode, depending on the output

current. When the average output current falls below the

PWM/PSM threshold, the buck regulator enters PSM mode

operation; in PSM mode, the regulator operates with a reduced

switching frequency to maintain high efficiency. The low-side

MOSFET turns off when the output current reaches 0 A, causing

the regulator to operate in discontinuous mode (DCM).

Use the CFG2 pin to configure the operational mode of all four

buck regulators to operate in PWM mode or automatic

PWM/PSM mode.

LOW NOISE ARCHITECTURE

Traditional dc-to-dc or linear regulator output noise is typically

proportional to the output voltage setting. The ADP5014 optimizes

many analog blocks to achieve lower output noise at low frequency

range. The unity-gain voltage reference structure also makes its

output noise independent from the output voltage setting when

VOUT setting is less than VREF voltage.

The low noise buck regulator enables the device to power up noise

sensitive signal chain products directly with excellent output noise

performance, ~25 μV rms from 10 Hz to 100 kHz, which is similar

or even better than traditional low dropout regulators (LDOs).

The additional LC filter is still required because the fundamental

switching output ripple and its harmonic affects signal chain

performance and likely generates unexpected spurs. This

additional LC filter is typically relatively small due to the high

switching frequency operation of the buck regulator in the

ADP5014.

INTERNAL REFERENCE (VREF)

The ADP5014 provides an accurate, low noise, 2.0 V reference

voltage. One 0.47 μF ceramic capacitor must be connected

between VREF and ground. A larger value of capacitance provides

better noise suppression.

The VREF reference circuitry is mainly designed for internal use

and has very limited output load capacity (<1 mA); therefore,

check the load capability requirements if VREF is used for other

purposes.

ADJUSTABLE OUTPUT VOLTAGE

The ADP5014 provides adjustable output voltage settings via

the external resistor divider. To minimize output noise and

maintain the loop unity-gain, the device provides the reference

input path to the error amplifier input with the integrated low-

frequency filter for each channel. Use an external resistor

divider to set the desired output voltage. Figure 28 shows the

adjustable output voltage diagram.

BUCK

COUTx

VSETx

SWx

PVINx

VREF

VFBx

VOUTx

RTOP

RBOT

Figure 28. Adjustable Output Voltage Configuration

ADP5014ACPZ-R7 数据表(PDF) 14 Page - Analog Devices

ADP5014ACPZ-R7 数据表(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

数据表下载