ADP5014ACPZ-R7 datasheet(16/34 Pages) AD

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ADP5014

Data Sheet

Rev. A | Page 16 of 34

PARALLEL OPERATION

The ADP5014 supports 2-phase parallel operation of Channel 1

and Channel 2 to provide a single output with up to 8 A of

current, and two-phase parallel operation of Channel 3 and

Channel 4 to provide a single output with up to 4 A of current.

To configure a 2-phase single output in parallel operation,

perform the following steps (see Figure 29). Use the CFG1 pin

to select parallel operation as specified in Table 7.



Leave the COMP2 pin (or COMP4 pin) open.



Use the VSET1 and FB1 pin (or VSET3 and FB3 pin) to set

the output voltage.



Connect the FB2 and VSET2 pin (or FB4 pin and VSET4)

to ground (FB2 is ignored). Connect the EN2/DL12 pin (or

EN4/DL34 pin) to ground in manual enable mode (EN2 is

ignored). Note that the EN2/DL12 pin is for the delay timer

configuration in sequence enable mode.

CH1

BUCK

(4A)

CH2

BUCK

(4A)

FB1

PVIN1

VIN

EN1

EN2

COMP1

VSET1

SW1

FB2

SW2

PVIN2

COMP2

VREF

VSET2

CFG1

VOUT

(UP TO 8A)

Figure 29. Parallel Operation for Channel 1 and Channel 2

The following considerations apply when two channels are

operating in the parallel configuration:



The input voltages for both channels are the same.



Both channels are operating in forced PWM mode.



Do not support sequence mode.

The current balance in parallel configuration is well regulated

by the internal control loop. Figure 30 shows the typical current

balance matching in the parallel output configuration.

TOTAL OUTPUT LOAD (A)

024

CHANNEL 1 CURRENT

CHANNEL 2 CURRENT

Figure 30. Current Balance in Parallel Output Configuration, VIN = 5 V,

VOUT = 1.2 V, fSW = 1.2 MHz, FPWM Mode

MANUAL/SEQUENCE MODE

The ADP5014 features two enable modes using the CFG2 pin

configuration. The manual mode has individual precision

enable pins to enable each regulator manually. Alternatively,

the sequence mode has one grouped precision enable signal

with a programmable power-up and power-down delay timer on

each rail.

The enable pin (EN1 to EN4) functionality is different in

manual mode and sequence mode. Note that throughout this

data sheet, multifunction pins, such as EN1/ENALL, are referred to

by either the entire pin name or by a single function of the pin, for

example, EN1, when only that format is relevant. Figure 31 and

Table 8 show the pin mapping in different enable modes.

If some channels are unused, pull down the corresponding

PVINx and ENx pin to ground and leave the SWx, COMPx,

VSETx, and FBx pins floating.

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

VOUT1

VOUT2

VOUT3

VOUT4

EN1

EN2

EN3

EN4

GPIO

VOUT1

VOUT2

VOUT3

VOUT4

MANUAL ENABLE

MODE

DL12

DL34

GPIO

–

0.6V

SEQUENCE ENABLE

MODE

ENALL

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

Figure 31. Pin Configuration in Different Enable Modes

Table 8. Pin Functionality in Different Enable Modes

Pin Name

Manual Enable Mode

Sequence Enable Mode

EN1/ENALL (Pin 17)

EN1—enable pin for Channel 1

ENALL—grouped enable pin for all four channels

EN2/DL12 (Pin 16)

EN2—enable pin for Channel 2

DL12—delay timer setting for Channel 1 and Channel 2

EN3/UV (Pin 13)

EN3—enable pin for Channel 3

UV—undervoltage comparator input

EN4/DL34 (Pin 12)

EN4—enable pin for Channel 4

DL34—delay timer setting for Channel 3 and Channel 4

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