ADP5014ACPZ-R7 datasheet(20/34 Pages) AD

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ADP5014

Data Sheet

Rev. A | Page 20 of 34

SOFT START

The buck regulators in the ADP5014 include soft start circuitry

that ramps the output voltage in a controlled manner during

startup, thereby limiting the inrush current. The soft start time

for all channels is typically fixed at 2 ms. The soft start time for

all channels can be increased by eight times using the CFG2 pin

configuration.

STARTUP WITH PRECHARGED OUTPUT

The buck regulators in the ADP5014 include a precharged

startup feature to protect the low-side FETs from damage

during startup. If the output voltage is precharged before the

regulator is turned on, the regulator prevents reverse inductor

current, which discharges the output capacitor, until the

internal soft start reference voltage exceeds the precharged

voltage on a feedback (FBx) pin.

CURRENT-LIMIT PROTECTION

The buck regulators in the ADP5014 include peak current-limit

protection circuitry to limit the amount of positive current

flowing through the high-side MOSFET switch. The peak

current limit on the power switch limits the amount of current

that can flow from the input to the output. The programmable

current-limit threshold feature allows the use of small size

inductors for low current applications.

To configure different output load capability, connect a resistor

from the CFG1 pin to ground according to Table 6 which lists

different output current capability settings for all channels.

The buck regulators in the ADP5014 include negative current-

limit protection circuitry to limit certain amounts of negative

current flowing through the low-side MOSFET switch.

FREQUENCY FOLD BACK

The buck regulators in the ADP5014 include frequency fold

back to prevent output current runaway when a hard short

occurs on the output. Frequency fold back is implemented as

follows:

•

If the voltage at the FBx pin falls below half of the target

output voltage, the switching frequency is reduced by half.

•

If the voltage at the FBx pin falls again to below one-fourth

of the target output voltage, the switching frequency is

reduced by half of its current value again, equaling one-

fourth of fSW.

The reduced switching frequency allows more time for the

inductor current to decrease, but also increases the ripple

current during peak current regulation. The reduced switching

frequency results in a reduction in average current and prevents

output current runaway.

SHORT-CIRCUIT PROTECTION (SCP)

The buck regulators in the ADP5014 include a hiccup mode for

OCP. When the peak inductor current reaches the current-limit

threshold, the high-side MOSFET turns off and the low-side

MOSFET turns on until the next cycle.

When hiccup mode is active, the overcurrent fault counter is

incremented. If the overcurrent fault counter reaches 15 and

overflows (indicating a short-circuit condition), both the high-side

and low-side MOSFETs are turned off. The buck regulator

remains in hiccup mode for a period equal to seven soft start

cycles and then attempts to restart from soft start. If the short-

circuit fault has cleared, the regulator resumes normal operation;

otherwise, it reenters hiccup mode after the soft start.

Hiccup detection is masked during the initial soft start cycle to

enable startup of the buck regulator under heavy load conditions.

Careful design and proper component selection are required to

ensure the buck regulator recovers from hiccup mode under

heavy loads.

In parallel operation, the overcurrent protection in either

channel triggers both master and slave channels entering and

exiting the hiccup protection together.

OVERVOLTAGE PROTECTION

The ADP5014 includes an overvoltage protection feature to

protect the regulator against an output short to a higher voltage

supply, or when a strong load disconnect transient occurs. If the

feedback voltage increases to 1.15

×VSETx,theinternalhigh-

side and low-side MOSFETs are turned off until the voltage at

the FBx pin decreases to 1.1

×VSETxAtthattime,the

ADP5014 resumes normal operation.

UNDERVOLTAGE LOCKOUT

UVLO circuitry monitors the input voltage level of each buck

regulator, including the analog input pin in the ADP5014. If

any input voltage (PVINx pin) falls below 2.40 V (typical), the

corresponding channel is turned off. After the input voltage rises

above 2.65 V (typical), the soft start period is initiated, and the

corresponding channel is enabled when the ENx pin is high.

A UVLO condition on the AVIN pin has a higher priority than

a UVLO condition on individual channels, which means the

AVIN pin supply must be available before individual channels

can be operated.

The ADP5014 supports separate input voltages for buck

regulators. This means that the input voltages for each

individual buck regulator can be connected to different supply

voltages, as long as its input voltage (PVINx pin) and its AVIN pin

voltage are above its UVLO threshold.

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