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ADP5014ACPZ-R7 数据表(PDF) 30 Page - Analog Devices |
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ADP5014ACPZ-R7 数据表(HTML) 30 Page - Analog Devices |
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30 / 34 page  ADP5014 Data Sheet Rev. A | Page 30 of 34 PCB LAYOUT RECOMMENDATIONS Good circuit board layout is essential to obtain the best performance from the ADP5014 (see Figure 45). Poor layout can affect the regulation and stability of the device, as well as the EMI and electromagnetic compatibility (EMC) performance. Refer to the following guidelines for a good PCB layout. • Place the input capacitor, inductor, and output capacitor close to the IC. • Use short, thick traces to connect the input capacitors to the PVINx pins, and use dedicated power ground to connect the input and output capacitor grounds to minimize the connection length. • Use several high current vias, if required, to connect PVINx, PGNDx, or SWx to other power planes. • Use short, thick traces to connect the inductors to the SWx pins and the output capacitors. • Ensure that the high current loop traces are as short and wide as possible. • Maximize the amount of ground metal for the exposed pad, and use as many vias as possible on the component side to improve thermal dissipation. • Use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes. • Place the decoupling capacitors close to the VREF pin. • Place the RC filter close to the AVIN pin. • Place the frequency setting resistor close to the RT pin. • Place the VREF resistor divider close to the VSETx and the feedback resistor divider close to the FBx pin. In addition, keep the VSETx and FBx traces away from the high current traces and the switch node to avoid noise pickup. • Use size 0402 or 0603 resistors and capacitors to achieve the smallest possible footprint solution on boards where space is limited. 47µF 6.3V/XR5 0603 47µF 6.3V/XR5 0603 VOUT1 VOUT2 47µF 6.3V/XR5 0805 47µF 6.3V/XR5 0805 47µF 6.5V/XR5 0805 47µF 6.3V/XR5 0805 R0402 R0402 R0402 R0402 R0402 R0402 ADP5014 6mm × 6mm 30 29 28 27 26 25 24 23 22 21 VSET4 FB3 FB4 VSET3 VREF VSET2 VSET1 RT AVIN FB1 COMP1 PVIN1 PVIN1 SW1 PVIN2 GPIO EN4/ DL34 EN3/UV CFG2 CFG1 EN2/ DL12 EN1/ ENALL FB2 COMP2 COMP3 PVIN3 SW3 PGND3 PGND4 SW4 PVIN4 COMP4 SW1 PGND1 PGND1 PGND2 PGND2 SW2 SW2 PVIN2 1 2 3 4 5 6 7 8 9 10 Figure 45. Typical PCB Layout for the ADP5014 |
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