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EDBA164B4PR-1DATF-R 数据表(PDF) 104 Page - Micron Technology |
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EDBA164B4PR-1DATF-R 数据表(HTML) 104 Page - Micron Technology |
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104 / 152 page  Table 62: Switching for IDD4R (Continued) Clock CKE CS_n Clock Cycle Number Command CA[2:0] CA[9:3] All DQ Falling H H N + 3 NOP HLH LHLHLHL L Notes: 1. Data strobe (DQS) is changing between HIGH and LOW with every clock cycle. 2. The noted pattern (N, N + 1...) is used continuously during IDD measurement for IDD4R. Table 63: Switching for IDD4W Clock CKE CS_n Clock Cycle Number Command CA[2:0] CA[9:3] All DQ Rising H L N Write_Rising HLL LHLHLHL L Falling H L N Write_Falling LLL LLLLLLL L Rising H H N +1 NOP LLL LLLLLLL H Falling H H N + 1 NOP HLH HLHLLHL L Rising H L N + 2 Write_Rising HLL HLHLLHL H Falling H L N + 2 Write_Falling LLL HHHHHHH H Rising H H N + 3 NOP LLL HHHHHHH H Falling H H N + 3 NOP HLH LHLHLHL L Notes: 1. Data strobe (DQS) is changing between HIGH and LOW with every clock cycle. 2. Data masking (DM) must always be driven LOW. 3. The noted pattern (N, N + 1...) is used continuously during IDD measurement for IDD4W. Table 64: IDD Specification Parameters and Operating Conditions Notes 1–3 apply to all parameters and conditions Parameter/Condition Symbol Power Supply Notes Operating one bank active-precharge current (SDRAM): tCK = tCKmin; tRC = tRCmin; CKE is HIGH; CS_n is HIGH between valid commands; CA bus in- puts are switching; Data bus inputs are stable IDD01 VDD1 IDD02 VDD2 IDD0in VDDQ 4 Idle power-down standby current: tCK = tCKmin; CKE is LOW; CS_n is HIGH; All banks are idle; CA bus inputs are switching; Data bus inputs are sta- ble IDD2P1 VDD1 IDD2P2 VDD2 IDD2P,in VDDQ 4 Idle power-down standby current with clock stop: CK_t = LOW, CK_c = HIGH; CKE is LOW; CS_n is HIGH; All banks are idle; CA bus inputs are stable; Data bus inputs are stable IDD2PS1 VDD1 IDD2PS2 VDD2 IDD2PS,in VDDQ 4 Idle non-power-down standby current: tCK = tCKmin; CKE is HIGH; CS_n is HIGH; All banks are idle; CA bus inputs are switching; Data bus inputs are sta- ble IDD2N1 VDD1 IDD2N2 VDD2 IDD2N,in VDDQ 4 216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM Electrical Specifications – IDD Specifications and Conditions 09005aef85eb530a 216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN 104 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. |
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