AM486DX2 datasheet(19/67 Pages) AMD

19 / 67 page

Am5X86 Microprocessor

AMD

PRELIMINARY

hanced system support because the cache may contain

data that is not identical to data in main memory at the

same address location.

4.5

Write-Back Cache Protocol

The Am5X86 microprocessor family write-back cache

coherency protocol reduces bus activity while maintain-

ing data coherency in a multimaster environment. The

cache coherency protocol offers the following advan-

tages:

s No unnecessary bus traffic. The protocol dynamical-

ly identifies shared data to the granularity of a cache

line. This dynamic identification ensures that the traf-

fic on the external bus is the minimum necessary to

ensure coherency.

s Software-transparent. Because the protocol gives

the appearance of a single, unified memory, soft-

ware does not have to maintain coherency or identify

shared data. Application software developed for a

system without a cache can run without modification.

Software support is required only in the operating

system to identify non-cacheable data regions.

The Am5X86 microprocessor family implements a mod-

ified MESI protocol on systems with write-back cache

support. MESI allows a cache line to exist in four states:

modified, exclusive, shared, and invalid. The Am5X86

microprocessor family allocates memory in the cache

due to a read miss. Write allocation is not implemented.

To maintain coherency between cache and main mem-

ory, the MESI protocol has the following characteristics:

s The system memory is always updated during a

snoop when a modified line is hit.

s If a modified line is hit by another master during

snooping, the master is forced off the bus and the

snooped cache writes back the modified line to the

system memory. After the snooped cache completes

the write, the forced-off bus master restarts the ac-

cess and reads the modified data from memory.

4.5.1

Cache Line Overview

To implement the Am5X86 microprocessor cache co-

herency protocol, each tag entry is expanded to 2 bits:

S1 and S0. Each tag entry is associated with a cache

line. Table 3 shows the cache line organization.

Table 3. Cache Line Organization

Data Words (32 Bits)

Address Tag and Status

Address Tag, S1, S0

4.5.2

Line Status and Line State

A cache line can occupy one of four legal states as

indicated by bits S0 and S1. The line states are shown

in Table 4. Each line in the cache is in one of these

states. The state transition is induced either by the pro-

cessor or during snooping from an external bus master.

4.5.2.1

Invalid

An invalid cache line does not contain valid data for any

external memory location. An invalid line does not par-

ticipate in the cache coherency protocol.

4.5.2.2

Exclusive

An exclusive line contains valid data for some external

memory location. The data exactly matches the data in

the external memory location.

4.5.2.3

Shared

A shared line contains valid data for an external memory

location, the data is shared by another cache, and the

shared data matches the data in the external memory

exactly; or the cache line is in Write-through mode.

4.5.2.4

Modified

A modified line contains valid data for an external mem-

ory location. However, the data does not match the data

in the external location because the processor has mod-

ified the data since it was loaded from the external mem-

ory. A cache that contains a modified line is responsible

for ensuring that the data is properly maintained. This

means that in the case of an external access to that line

from another external bus master, the modified line is

first written back to the external memory before the other

external bus master can complete its access. Table 5

shows the MESI cache line states and the correspond-

ing availability of data.

Table 4. Legal Cache Line States

Line State

Invalid

Exclusive

Modified

Shared

AM486DX2 数据表(PDF) 19 Page - Advanced Micro Devices

AM486DX2 数据表(HTML) 19 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

数据表下载