AM486DX2 datasheet(56/67 Pages) AMD

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Am5X86 Microprocessor

AMD

PRELIMINARY

Am5X86 CPU IDENTIFICATION

The Am5X86 microprocessor supports two standard

methods for identifying the CPU in a system. The re-

ported values are assigned based on the RESET status

of the WB/WT pin input (Low = write-through; High =

write-back).

10.1 DX Register at RESET

The DX register always contains a component identifier

at the conclusion of RESET. The upper byte of DX (DH)

contains 04 and the lower byte of DX (DL) contains a

CPU type/stepping identifier (see Table 19).

10.2 CPUID Instruction

The Am5X86 microprocessor family implements the

CPUID instruction that makes information available to

software about the family, model and stepping of the

microprocessor on which it is executing. Support of this

instruction is indicated by the presence of a user-mod-

ifiable bit in position EFLAGS.21, referred to as the

EFLAGS.ID bit. This bit is reset to zero at device reset

(RESET or SRESET) for compatibility with existing pro-

cessor designs.

10.2.1 CPUID Timing

CPUID execution timing depends on the selected EAX

parameter values (see Table 20).

10.2.2 CPUID Operation

The CPUID instruction requires the user to pass an input

parameter to the CPU in the EAX register. The CPU

response is returned to the user in registers EAX, EBX,

ECX, and EDX.

When the parameter passed in EAX is zero, the register

values returned upon instruction execution are:

The values in EBX, ECX, and EDX indicate an AMD

microprocessor. When taken in the proper order:

s EBX (least significant bit to most significant bit)

s EDX (least significant bit to most significant bit)

s ECX (least significant bit to most significant bit)

they decode to

AuthenticAMD

When the parameter passed in EAX is 1, the register

values returned are:

The value returned in EAX after CPUID instruction ex-

ecution is identical to the value loaded into EDX upon

device reset. Software must avoid any dependency

upon the state of reserved processor bits.

When the parameter passed in EAX is greater than one,

Table 19. CPU ID Codes

CLKMUL Setting/Cache mode

Component

ID (DH)

Revision

ID (DL)

Write-through mode

Write-back mode

Table 20. CPUID Instruction Description

Code

Instruction

EAX

Input

Value

CPU

Core

Clocks

Description

0F A2 CPUID

AMD string

CPU ID Register

null registers

EAX[31:0]

00000001h

EBX[31:0]

68747541h

ECX[31:0]

444D4163h

EDX[31:0]

69746E65h

EAX[3:0]

Stepping ID*

EAX[7:4]

model:

Am5X86 CPU:

Write-through mode = Eh

Write-back mode = Fh

EAX[11:8]

Family

486 Instruction Set = 4h

EAX[15:12]

0000

EAX[31:16]

RESERVED

EBX[31:0]

00000000h

ECX[31:0]

00000000h

EDX[31:0]

00000001h = all versions

The 1 in bit 0 indicates that the FPU

is present

Note:

*Please contact AMD at (800) 222-9323

for stepping ID details.

EAX[31:0]

00000000h

EBX[31:0]

00000000h

ECX[31:0]

00000000h

EDX[31:0]

00000000h

Flags affected: No flags are affected.

Exceptions: None

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