AM486DX2 datasheet(53/67 Pages) AMD

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Am5X86 Microprocessor

AMD

PRELIMINARY

Table 17. Test Register TR4 Bit Descriptions

30–29

27–26

25–24

23–22

21–20

19–16

15–12

9–7

6–3

2–0

Tag

Valid

LRU

Valid

(rd)

Not

used

Not

used

STn

Rsvd.

ST3

ST2

ST1

ST0

Reserved

Not used

Valid

LRU

Valid

(rd)

Not

used

EXT = 1

EXT = 0

Notes:

1. The values of STn and ST3–ST0 are: 00 = Invalid; 01 = Exclusive; 10 = Modified; 11 = Shared.

2. During a cache look-up, bit 11 is read only and always 0. The bit is read/write otherwise.

Table 18. Test Register TR5 Bit Descriptions

31–20

18–17

15–12

11–4

3–2

1–0

Write-Back

Not used

Ext

Set State

Reserved

Not used

Index

Entry

Control

Write-Through

Not used

Index

Entry

Control

Notes:

1. Bit 19 in TR5 is EXT. If EXT = 0, TR4 has the standard 486 processor definition for write-through cache.

2. The values of Set State are: 00 = Invalid; 01 = Exclusive; 10 = Modified; 11 = Shared.

pushed onto the stack. If the offset of the interrupted

procedure is greater than 64 Kbytes, it is not possi-

ble for the interrupt/exception handler to return con-

trol to that procedure. (One work-around is to

perform software adjustment of the return address

on the stack.)

The SMBASE Relocation feature affects the way

the CPU returns from an interrupt or exception dur-

ing an SMI handler.

Note: The execution of an IRET instruction enables

Non-Maskable Interrupt (NMI) processing.

7.9.3

Halt during SMM

HALT should not be executed during SMM, unless in-

terrupts have been enabled. Interrupts are disabled on

entry to SMM. INTR and NMI are the only events that

take the CPU out of HALT within SMM.

7.9.4

Relocating SMRAM to an Address above

1 Mbyte

Within SMM (or Real mode), the segment base registers

can be updated only by changing the segment register.

The segment registers contain only 16 bits, which allows

only 20 bits to be used for a segment base address (the

segment register is shifted left 4 bits to determine the

segment base address). If SMRAM is relocated to an

address above 1 Mbyte, the segment registers can no

longer be initialized to point to SMRAM.

These areas can still be accessed by using address

override prefixes to generate an offset to the correct

address. For example, if the SMBASE has been relo-

cated immediately below 16 Mbytes, the DS and ES

registers are still initialized to 0000 0000h. Data in SM-

RAM can still be accessed by using 32-bit displacement

registers

move esi,OOFFxxxxh

;64K segment

immediately below 16M

move ax,ds:[esi]

TEST REGISTERS 4 AND 5

MODIFICATIONS

The Cache Test Registers for the Am5X86 microproces-

sor are the same test registers (TR3, TR4, and TR5)

provided in Am486 microprocessors. TR3 is the cache

test data register. TR4, the cache test status register,

and TR5, the cache test control register, operate togeth-

er with TR3.

If WB/WT meets the necessary setup timing and is sam-

pled Low on the falling edge of RESET, the processor

is placed in Write-through mode and the test register

function is identical to the Am486 microprocessors. If

WB/WT meets the necessary setup timing and is sam-

pled High on the falling edge of RESET, the processor

is placed in Write-back mode and the test registers TR4

and TR5 are modified to support the added write-back

cache functionality. Tables 17 and 18 show the individ-

ual bit functions of these registers. Sections 8.1 and 8.2

provide a detailed description of the field functions.

Note: TR3 has the same functions in both Write-through

and Write-back modes.These functions are identical to

the TR3 register functions provided by Am486 micro-

processors.

8.1

TR4 Definition

This section includes a detailed description of the bit

fields defined for TR4.

Note: Bits listed in Table 17 as Reserved or Not used

are not included in these descriptions.

s Tag (bits 31–12): Read/Write, always available in

Write-through mode. Available only when EXT=0 in

TR5 in Write-back mode. For a cache write, this is

the tag that specifies the address in memory. On a

cache look-up, this is tag for the selected entry in the

cache.

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