AM486DX2 datasheet(20/67 Pages) AMD

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Am5X86 Microprocessor

AMD

PRELIMINARY

4.6

Cache Replacement Description

The cache line replacement algorithm uses the standard

Am486 CPU pseudo LRU (Least-Recently Used) strat-

egy. When a line must be placed in the internal cache,

the microprocessor first checks to see if there is an in-

valid line available in the set. If no invalid line is available,

the LRU algorithm replaces the least-recently used

cache line in the four-way set with the new cache line.

If the cache line for replacement is modified, the modi-

fied cache line is placed into the copy-back buffer for

copying back to external memory, and the new cache

line is placed into the cache. This copy-back ensures

that the external memory is updated with the modified

data upon replacement.

4.7

Memory Configuration

In computer systems, memory regions require specific

caching and memory write methods. For example, some

memory regions are non-cacheable while others are

cacheable but are write-through. To allow maximum

memory configuration, the microprocessor supports

specific memory region requirements. All bus masters,

such as DMA controllers, must reflect all data transfers

on the microprocessor local bus so that the micropro-

cessor can respond appropriately.

4.7.1

Cacheability

The Am5X86 CPU caches data based on the state of

the CD and NW bits in CR0, in conjunction with the KEN

signal, at the time of a burst read access from memory.

If the WB/WT signal is Low during the first BRDY, KEN

meets the standard setup and hold requirements and

the four 32-bit doublewords are still placed in the cache.

However, all cacheable accesses in this mode are con-

sidered write-through. When the WB/WT is High during

the first BRDY, the entire four 32-bit doubleword transfer

is considered write-back.

Note: The CD bit in CR0 enables (0) or disables (1) the

internal cache. The NW bit in CR0 enables (0) or dis-

ables (1) write-through and snooping cycles. RESET

sets CD and NW to 1. Unlike RESET, however, SRESET

does not invalidate the cache nor does it modify the

values of CD and NW in CR0.

4.7.2

Write-Through/Write-Back

If the CPU is operating in Write-back mode (i.e., the

⁄WT pin was sampled High at RESET), the WB⁄WT

pin indicates whether an individual write access is exe-

cuted as write-through or write-back. The Am5X86 mi-

croprocessor does this on an access-by-access basis.

Once the cache line is in the cache, the STATUS bit is

tested each time the processor writes to the cache line

or a tag compare results in a hit during Bus-watching

mode. If the WB

⁄WT signal is Low during the first BRDY

of the cache line read access, the cache line is consid-

ered a write-through access. Therefore, all writes to this

location in the cache are reflected on the external bus,

even if the cache line is write protected.

4.8

Cache Functionality in Write-Back

Mode

The description of cache functionality in Write-back

mode is divided into two sections: processor-initiated

cache functions and snooping actions.

4.8.1

Processor-Initiated Cache Functions and

State Transitions

The microprocessor contains two new buffers for use

with the MESI protocol support: the copy-back buffer

and the write-back buffer. The processor uses the copy-

back buffer for cache line replacement of modified lines.

The write-back buffer is used when an external bus mas-

ter hits a modified line in the cache during a snoop op-

eration and the cache line is designated for write-back

to main memory. Each buffer is four doublewords in size.

Figure 1 shows a diagram of the state transitions in-

duced by the local processor. When a read miss occurs,

the line selected for replacement remains in the modified

state until overwritten. A copy of the modified line is sent

to the copy-back buffer to be written back after replace-

ment. When reload has successfully completed, the line

is set either to the exclusive or the shared state, depend-

ing on the state of PWT and WB/WT signals.

Table 5. MESI Cache Line Status

Situation

Modified Exclusive

Shared

Invalid

Line valid? Yes

Yes

External

memory

is...

out-of-

date

valid

status

unknown

A write to

this cache

line...

does not

go to the

bus

does not go

to the bus

goes to

the bus

and

updates

goes

directly to

the bus

Invalid

Shared

Modified

Exclusive

Read_Hit

Read_Miss

(WB/WT = 1)

•

(PWT = 0)

Read_Miss

[(WB/WT = 0) + (PWT = 1)]

Write_Hit

Write_Hit + Read_Hit

Shared

Read_Hit

+ Write_Hit

Figure 1. Processor-Induced Line Transitions in

Write-Back Mode

Note: Write_Hit

generates external

bus cycle.

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