AM486DX2 datasheet(46/67 Pages) AMD

46 / 67 page

Am5X86 Microprocessor

AMD

PRELIMINARY

7.7.1

Exceptions and Interrupts with System

Management Mode

When the CPU enters SMM, it disables INTR interrupts,

debug, and single step traps by clearing the EFLAGS,

DR6, and DR7 registers. This prevents a debug appli-

cation from accidentally breaking into an SMI handler.

This is necessary because the SMI handler operates

from a distinct address space (SMRAM) and the debug

trap does not represent the normal system memory

space.

For an SMI handler to use the debug trap feature of the

processor to debug SMI handler code, it must first en-

sure that an SMM-compliant debug handler is available.

The SMI handler must also ensure DR3–DR0 is saved

to be restored later. The debug registers DR3–DR0 and

DR7 must then be initialized with the appropriate values.

For the processor to use the single step feature of the

processor, it must ensure that an SMM-compliant single

step handler is available and then set the trap flag in the

EFLAGS register. If the system design requires the pro-

cessor to respond to hardware INTR requests while in

SMM, it must ensure that an SMM-compliant interrupt

handler is available, and then set the interrupt flag in the

EFLAGS register (using the STI instruction). Software

interrupts are not blocked on entry to SMM, and the

system software designer must provide an SMM-com-

pliant interrupt handler before attempting to execute any

software interrupt instructions. Note that in SMM mode,

the interrupt vector table has the same properties and

location as the Real mode vector table.

NMI interrupts are blocked on entry to the SMI handler.

If an NMI request occurs during the SMI handler, it is

latched and serviced after the processor exits SMM.

Only one NMI request is latched during the SMI handler.

If an NMI request is pending when the processor exe-

cutes the RSM instruction, the NMI is serviced before

the next instruction of the interrupted code sequence.

Although NMI requests are blocked when the CPU en-

ters SMM, they may be enabled through software by

executing an IRET instruction. If the SMI handler re-

quires the use of NMI interrupts, it should invoke a dum-

my interrupt service routine to execute an IRET

instruction. When an IRET instruction is executed, NMI

interrupt requests are serviced in the same Real mode

manner in which they are handled outside of SMM.

7.7.2

SMM Revisions Identifier

The 32-bit SMM Revision Identifier specifies the version

of SMM and the extensions that are available on the

processor. The fields of the SMM Revision Identifiers

and bit definitions are shown in Table 13 and Table 14.

Bit 17 or 16 indicates whether the feature is supported

(1=supported, 0=not supported). The processor always

reads the SMM Revision Identifier at the time of a re-

store. The I/O Trap Extension and SMM Base Reloca-

tion bits are fixed. The processor writes these bits out

at the time it performs a save state.

Note: Changing the state of the reserved bits may result

in unpredictable processor behavior.

Table 13. SMM Revision Identifier

31–18

15–0

Reserved

SMM Base

Relocation

I/O Trap

Extension

SMM Revision Level

00000000000000

0000h

Table 14. SMM Revision Identifier Bit Definitions

Bit Name

Description

Default

State

State at

SMM

Entry

State at

SMM Exit

Notes

SMM Base

Relocation

1=SMM Base Relocation Available

0=SMM Base Relocation

Unavailable

No Change in State

I/O Trap Extension

1=I/O Trapping Available

0=I/O Trapping Unavailable

No Change in State

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