AM486DX2 datasheet(45/67 Pages) AMD

45 / 67 page

Am5X86 Microprocessor

AMD

PRELIMINARY

Note:

Interrupts from INT and NMI are disabled on SMM entry.

The following is a summary of the key features in the

SMM environment:

s Real mode style address calculation

s 4-Gbyte limit checking

s IF flag is cleared

s NMI is disabled

s TF flag in EFLAGS is cleared; single step traps are

disabled

s DR7 is cleared; debug traps are disabled

s The RSM instruction no longer generates an invalid

opcode error

s Default 16-bit opcode, register, and stack use

s All bus arbitration (HOLD, AHOLD, BOFF) inputs,

and bus sizing (BS8, BS16) inputs operate normally

while the CPU is in SMM

7.7

Executing System Management

Mode Handler

The processor begins execution of the SMI handler at

offset 8000h in the CS segment. The CS Base is initially

30000h, as shown in Table 12.

Notes:

1. The segment limit check is 4 Gbytes instead of the usual

64 Kbytes.

2. The Selector value for CS remains at 3000h even if the

SMBASE is changed.

The CS Base can be changed using the SMM Base

relocation feature

. When the SMI handler is invoked,

the CPU’s PE and PG bits in CR0 are reset to 0. The

processor is in an environment similar to Real mode,

but without the 64-Kbyte limit checking. However, the

default operand size and the default address size are

set to 16 bits. The EM bit is cleared so that no exceptions

are generated. (If the SMM was entered from Protected

mode, the Real mode interrupt and exception support

is not available.) The SMI handler should not use float-

ing-point unit instructions until the FPU is properly de-

tected (within the SMI handler) and the exception

support is initialized.

Because the segment bases (other than CS) are cleared

to 0 and the segment limits are set to 4 Gbytes, the

address space may be treated as a single flat 4-Gbyte

linear space that is unsegmented. The CPU is still in

Real mode and when a segment selector is loaded with

a 16-bit value, that value is then shifted left by 4 bits and

loaded into the segment base cache.

In SMM, the CPU can access or jump anywhere within

the 4-Gbyte logical address space. The CPU can also

indirectly access or perform a near jump anywhere with-

in the 4-Gbyte logical address space.

Table 11. SMM Initial CPU Core Register Settings

SMM Initial State

General Purpose

Registers

Unmodified

EFLAGS

0000 0002h

CR0

Bits 0, 2, 3, and 31 cleared (PE, EM, TS,

and PG); rest unmodified

DR6

Unpredictable state

DR7

0000 0400h

GDTR, LDTR,

IDTR, TSSR

Unmodified

EIP

0000 8000h

Table 12. Segment Register Initial States

Segment

Selector

Base

Attributes

Limit1

CS2

3000h

30000h

16-bit,

expand up

4 Gbytes

0000h

00000000h

16-bit,

expand up

4 Gbytes

0000h

00000000h

16-bit,

expand up

4 Gbytes

0000h

00000000h

16-bit,

expand up

4 Gbytes

0000h

00000000h

16-bit,

expand up

4 Gbytes

0000h

00000000h

16-bit,

expand up

4 Gbytes

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