AM486DX2 datasheet(41/67 Pages) AMD

41 / 67 page

Am5X86 Microprocessor

AMD

PRELIMINARY

For uses such as fast enabling of external I/O devices,

the SMSAVE mode permits the restarting of the I/O in-

structions and the HALT instruction. This is accom-

plished through I/O Trap Restart and Halt/Auto HALT

Restart slots. Only I/O and HALT opcodes are restart-

able. Attempts to restart any other opcode may result

in unpredictable behavior.

The System Management Interrupt hardware interface

consists of the SMI request input and the SMIACT output

used by the system to decode the SMRAM (see Figure

23).

7.3.1

System Management Interrupt Processing

SMI is a falling-edge-triggered, non-maskable interrupt

request signal. SMI is an asynchronous signal, but setup

and hold times must be met to guarantee recognition in

a specific clock. The SMI input does not have to remain

active until the interrupt is actually serviced. The SMI

input needs to remain active for only a single clock if the

required setup and hold times are met. SMI also works

correctly if it is held active for an arbitrary number of

clocks (see Figure 24).

The SMI input must be held inactive for at least four

clocks after it is asserted to reset the edge-triggered

logic. A subsequent SMI may not be recognized if the

SMI input is not held inactive for at least four clocks after

being asserted. SMI, like NMI, is not affected by the IF

bit in the EFLAGS register and is recognized on an in-

struction boundary. SMI does not break locked bus cy-

cles. SMI has a higher priority than NMI and is not

masked during an NMI. After SMI is recognized, the SMI

signal is masked internally until the RSM instruction is

executed and the interrupt service routine is complete.

Masking SMI prevents recursive calls. If another SMI

occurs while SMI is masked, the pending SMI is recog-

nized and executed on the next instruction boundary

after the current SMI completes. This instruction bound-

ary occurs before execution of the next instruction in the

interrupted application code, resulting in back-to-back

SMI handlers. Only one SMI signal can be pending while

SMI is masked. The SMI signal is synchronized inter-

nally and must be asserted at least three clock cycles

prior to asserting the RDY signal to guarantee recogni-

tion on a specific instruction boundary. This is important

for servicing an I/O trap with an SMI handler.

7.3.2

SMI Active (SMIACT)

SMIACT indicates that the CPU is operating in SMM.

The CPU asserts SMIACT in response to an SMI inter-

rupt request on the SMI pin. SMIACT is driven active

after the CPU has completed all pending write cycles

(including emptying the write buffers), and before the

first access to SMRAM when the CPU saves (writes) its

state (or context) to SMRAM. SMIACT remains active

until the last access to SMRAM when the CPU restores

(reads) its state from SMRAM. The SMIACT signal does

not float in response to HOLD. The SMIACT signal is

used by the system logic to decode SMRAM. The num-

ber of clocks required to complete the SMM state save

and restore is dependent on system memory perfor-

mance. The values shown in Figure 25 assume 0 wait-

state memory writes (2 clock cycles), 2–1–1–1 burst

read cycles, and 0 wait-state non-burst reads (two clock

cycles). Additionally, it is assumed that the data read

during the SMM state restore sequence is not cache-

able. The minimum time required to enter a SMSAVE

SMI handler routine for the CPU (from the completion

of the interrupted instruction) is given by:

Latency to start of SMl handler = A + B + C = 161 clocks

and the minimum time required to return to the interrupt-

ed application (following the final SMM instruction be-

fore RSM) is given by:

Latency to continue application = E + F + G = 258 clocks

CPU

SMIACT

SMI

SMI Interface

}

Figure 23. Basic SMI Hardware Interface

tsu

thd

SMI Sampled

CLK

CLK2

SMI

RDY

Figure 24. SMI Timing for Servicing an I/O Trap

AM486DX2 数据表(PDF) 41 Page - Advanced Micro Devices

AM486DX2 数据表(HTML) 41 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

数据表下载